公开(公告)号：US10069493B2

公开(公告)日：2018-09-04

申请号：US15299719

申请日：2016-10-21

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Veli Kartal ,  Alfons Graf

IPC: H03K17/00 ,  H03K17/94 ,  H01H1/00 ,  H03K17/042 ,  H03K17/082 ,  H02M3/07 ,  H03K17/687

Abstract: A circuit includes an electronic switch with an isolated gate, a measuring device for determining a charge at the isolated gate, and an energy supply for providing charge to the isolated gate based on the charge determined by the measuring device.

公开(公告)号：US09429598B2

公开(公告)日：2016-08-30

申请号：US14320143

申请日：2014-06-30

Applicant: Infineon Technologies AG

Inventor： Rainald Sander

IPC: G01R19/00 ,  G01R31/26

CPC classification number: G01R19/0092 ,  G01R31/2607 ,  G01R31/2639

Abstract: A semiconductor arrangement may include a multiplicity of semiconductor elements with controlling paths and controlled paths, the controlled paths having controllable conductivities and being connected parallel to each other. The semiconductor arrangement may also include a current evaluation circuit configured to measure current strengths of currents present in the controlled paths and to provide a signal representing the sum of the measured current strengths, and a control circuit connected to the controlling paths and configured to control the conductivities of the controlled paths in accordance with an input signal and the signal representing the sum of the current strengths. The at least one controlled path is controlled to have minimum conductivity if the signal representing the sum of the current strengths is below a threshold value.

Abstract translation: 半导体布置可以包括具有控制路径和受控路径的多个半导体元件，所述受控路径具有可控制的导电性并且彼此并联连接。 半导体布置还可以包括电流评估电路，其被配置为测量存在于受控路径中的电流的电流强度，并且提供表示所测量的电流强度之和的信号，以及连接到控制路径并被配置为控制 根据输入信号的受控路径的电导率和表示当前强度之和的信号。 如果表示电流强度之和的信号低于阈值，则至少一个受控路径被控制为具有最小的导电性。

公开(公告)号：US10290567B2

公开(公告)日：2019-05-14

申请号：US15694086

申请日：2017-09-01

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Liu Chen ,  Teck Sim Lee

IPC: H01L23/49 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.

公开(公告)号：US10277219B2

公开(公告)日：2019-04-30

申请号：US15639834

申请日：2017-06-30

Applicant: Infineon Technologies AG

Inventor： Rainald Sander ,  Andreas Meiser

IPC: H03K17/08 ,  H01L23/00

Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.