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    Configuration of integrated current flow sensor
    1.
    发明授权
    Configuration of integrated current flow sensor 有权

    公开(公告)号：US10802053B2

    公开(公告)日：2020-10-13

    申请号：US15273382

    申请日：2016-09-22

    Applicant: Infineon Technologies AG

    Inventor： Rainald Sander ,  Stephan Leisenheimer ,  Stefan Mieslinger

    IPC: G01R15/14 ,  H03K17/687

    Abstract: This disclosure is directed to techniques that may accurately determine the amount of current flowing through a power switch circuit by measuring the voltage across the inherent impedance of the circuit connections. One connection may include a low impedance connection between the power switch output and ground, where the low impedance connection may be on the order of milliohms. By using a four-wire measurement, the sensing connections are not in the current path, so the measured value may not be affected by the current. The connection that makes up the current path can be accomplished with a variety of conductive materials. Conductive materials may have a temperature coefficient of resistivity that may impact a measurement of electric current as the temperature changes. Measuring the temperature of the current path, along with the voltage across the connection, may allow a more accurate current measurement.

    CONFIGURATION OF INTEGRATED CURRENT FLOW SENSOR
    3.
    发明申请
    CONFIGURATION OF INTEGRATED CURRENT FLOW SENSOR 审中-公开

    公开(公告)号：US20180080957A1

    公开(公告)日：2018-03-22

    申请号：US15273382

    申请日：2016-09-22

    Applicant: Infineon Technologies AG

    Inventor： Rainald Sander ,  Stephan Leisenheimer ,  Stefan Mieslinger

    IPC: G01R15/14 ,  H03K17/687

    CPC classification number: G01R15/146 ,  H03K17/6871

    Abstract: This disclosure is directed to techniques that may accurately determine the amount of current flowing through a power switch circuit by measuring the voltage across the inherent impedance of the circuit connections. One connection may include a low impedance connection between the power switch output and ground, where the low impedance connection may be on the order of milliohms. By using a four-wire measurement, the sensing connections are not in the current path, so the measured value may not be affected by the current. The connection that makes up the current path can be accomplished with a variety of conductive materials. Conductive materials may have a temperature coefficient of resistivity that may impact a measurement of electric current as the temperature changes. Measuring the temperature of the current path, along with the voltage across the connection, may allow a more accurate current measurement.

    CURRENT MEASUREMENT IN A POWER SEMICONDUCTOR ARRANGEMENT
    4.
    发明申请
    CURRENT MEASUREMENT IN A POWER SEMICONDUCTOR ARRANGEMENT 有权
    功率半导体装置中的电流测量

    公开(公告)号：US20150377931A1

    公开(公告)日：2015-12-31

    申请号：US14320143

    申请日：2014-06-30

    Applicant: Infineon Technologies AG

    Inventor： Rainald Sander

    IPC: G01R19/00

    CPC classification number: G01R19/0092 ,  G01R31/2607 ,  G01R31/2639

    Abstract: A semiconductor arrangement may comprise a multiplicity of semiconductor elements with controlling paths and controlled paths, the controlled paths having controllable conductivities and being connected parallel to each other. The semiconductor arrangement may also comprise a current evaluation circuit configured to measure current strengths of currents present in the controlled paths and to provide a signal representing the sum of the measured current strengths, and a control circuit connected to the controlling paths and configured to control the conductivities of the controlled paths in accordance with an input signal and the signal representing the sum of the current strengths, wherein at least one controlled path is controlled to have minimum conductivity if the signal representing the sum of the current strengths is below a threshold value.

    Abstract translation: 半导体布置可以包括具有控制路径和受控路径的多个半导体元件，受控路径具有可控制的导电性并且彼此并联连接。 半导体布置还可以包括电流评估电路，其被配置为测量存在于受控路径中的电流的电流强度，并且提供表示所测量的电流强度之和的信号，以及连接到控制路径并被配置为控制 根据输入信号和表示电流强度之和的信号的受控路径的电导率，其中如果表示电流强度之和的信号低于阈值，则控制至少一个受控路径具有最小的导电性。

    SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING A SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING A SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230131909A1

    公开(公告)日：2023-04-27

    申请号：US18045393

    申请日：2022-10-10

    Applicant: Infineon Technologies AG

    Inventor： Rainald Sander ,  Lars Eckert ,  Fortunato Lopez

    IPC: H01L25/16 ,  H01L23/00 ,  H01L23/495

    Abstract: A semiconductor package comprises an encapsulation having a first lateral side and an opposite second lateral side, at least one power semiconductor chip having a drain contact region running along the first lateral side, a source contact region running along the second lateral side, and first and second inner contact regions arranged between the drain and source contact regions, a first external terminal which is connected to the drain contact region, is arranged centrally on the first lateral side, and is configured to apply a supply voltage for the at least one power semiconductor chip, a second external terminal which is connected to the source contact region, is arranged centrally on the second lateral side, and is configured to apply a reference voltage for the at least one power semiconductor chip, third and fourth external terminals which are connected to the first inner contact region. are arranged opposite each other at a first end of the first and second lateral sides, respectively, and are configured a first output of the semiconductor package, and fifth and sixth external terminals which are connected to the second inner contact region and are arranged opposite each other at a second end of the first and second lateral sides, respectively, and are configured as a second output of the semiconductor package.

    Electric circuit including a semiconductor device with a first transistor, a second transistor and a control circuit
    6.
    发明授权
    Electric circuit including a semiconductor device with a first transistor, a second transistor and a control circuit 有权

    公开(公告)号：US10468405B2

    公开(公告)日：2019-11-05

    申请号：US15418491

    申请日：2017-01-27

    Applicant: Infineon Technologies AG

    Inventor： Rainald Sander ,  Till Schloesser

    IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H03K17/687 ,  H01L27/06

    Abstract: An electric circuit includes a semiconductor device. The semiconductor device includes a first transistor and a second transistor in a common semiconductor substrate. The first transistor is of the same conductivity type as the second transistor. A first source region of the first transistor is electrically connected to a first source terminal via a first main surface of the semiconductor substrate. A second drain region of the second transistor is electrically connected to a second drain terminal via a first main surface of the semiconductor substrate. A first drain region of the first transistor and a second source region of the second transistor are electrically connected to an output terminal via a second main surface of the semiconductor substrate. The electric circuit further includes a control circuit operable to control a first gate electrode of the first transistor and a second gate electrode of the second transistor.

    Electronic Switching and Reverse Polarity Protection Circuit
    7.
    发明申请
    Electronic Switching and Reverse Polarity Protection Circuit 审中-公开

    公开(公告)号：US20180006639A1

    公开(公告)日：2018-01-04

    申请号：US15639834

    申请日：2017-06-30

    Applicant: Infineon Technologies AG

    Inventor： Rainald Sander ,  Andreas Meiser

    IPC: H03K17/08 ,  H01L23/00

    CPC classification number: H03K17/08 ,  H01L24/05 ,  H01L24/45 ,  H03K17/0822

    Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.

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