公开(公告)号：US20240056120A1

公开(公告)日：2024-02-15

申请号：US17819329

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Sashank KRISHNAMURTHY ,  Ofir DEGANI ,  Ashoke RAVI

IPC: H04B1/525 ,  H04B1/00 ,  H04B1/30

CPC classification number: H04B1/525 ,  H04B1/0078 ,  H04B1/30 ,  H04B2001/307

Abstract: A tunable bandpass low-noise amplifier (LNA). The LNA includes a plurality of N-path filters and a plurality of cascode amplifiers. The cascode amplifiers are configured to amplify an input signal. Each N-path filter is coupled to a different one of the plurality of cascode amplifiers. The plurality of N-path filters are driven by local oscillator (LO) signals having different frequencies, and output nodes of the plurality of cascode amplifiers are coupled in parallel. The frequencies of the LO signals may be symmetrically spaced around a desired frequency (fLO). Each N-path filter may be coupled to a source of the common-gate device of the coupled cascode amplifier. The LO signals may be generated by a digital-to-time converter (DTC)-based frequency synthesizer. The frequencies of the LO signals supplied to the N-path filters may be adjusted to tune the bandwidth of the bandpass LNA.

公开(公告)号：US20240048351A1

公开(公告)日：2024-02-08

申请号：US17641830

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashoke RAVI ,  Ronen KRONFELD ,  Ofir DEGANI

IPC: H04L7/033

CPC classification number: H04L7/0331

Abstract: A radio-frequency integrated circuit (RFIC) configured to generate a synthesized clock includes a phase locked loop (PLL) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ILCM) directly connected to a plurality of transceiver chains; wherein the PLL is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ILCMs; wherein the plurality of multiphase ILCMs are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.

公开(公告)号：US20230100670A1

公开(公告)日：2023-03-30

申请号：US17483880

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Alaa BEIDAS ,  Elan BANIN ,  Assaf BEN-BASSAT ,  Ofir DEGANI ,  Ashoke RAVI

IPC: G06N3/04 ,  G06N3/063

Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable oscillator configured to generate an oscillator signal. The spiking neuron may further include a circuit configured to obtain an integration value based on received input spike signals. The spiking neuron may further include a leakage circuit configured to obtain a leakage value based on the oscillator signal. The spiking neuron may further include an oscillator activator configured to activate or deactivate the triggerable oscillator based on the leakage value and the integration value.

公开(公告)号：US20220337292A1

公开(公告)日：2022-10-20

申请号：US17763209

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Sanket JAIN ,  Benjamin JANN ,  Ashoke RAVI ,  Satwik PATNAIK

IPC: H04B7/0413 ,  H04B7/26 ,  H04B7/01

Abstract: A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.