公开(公告)号：US20230090431A1

公开(公告)日：2023-03-23

申请号：US17810845

申请日：2022-07-06

Applicant: Intel Corporation

Inventor： Elan BANIN ,  Eytan MANN ,  Rotem BANIN ,  Ronen GERNIZKY ,  Ofir DEGANI ,  Igal KUSHNIR ,  Shahar PORAT ,  Amir RUBIN ,  Vladimir VOLOKITIN ,  Elinor KASHANI ,  Dmitry FELSENSTEIN ,  Ayal ESHKOLI ,  Tal DAVIDSON ,  Eng Hun OOI ,  Yossi TSFATI ,  Ran SHIMON

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20210265999A1

公开(公告)日：2021-08-26

申请号：US17059480

申请日：2019-08-05

Applicant: Intel Corporation

Inventor： Ofir DEGANI ,  Igal KUSHNIR ,  Elan BANIN ,  Rotem BANIN

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/091 ,  H03B5/32 ,  H04B1/04

Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.

公开(公告)号：US20250167818A1

公开(公告)日：2025-05-22

申请号：US18655458

申请日：2024-05-06

Applicant: Intel Corporation

Inventor： Elan BANIN ,  Eytan MANN ,  Rotem BANIN ,  Ronen GERNIZKY ,  Ofir DEGANI ,  Igal KUSHNIR ,  Shahar PORAT ,  Amir RUBIN ,  Vladimir VOLOKITIN ,  Elinor KASHANI ,  Dmitry FELSENSTEIN ,  Ayal ESHKOLI ,  Tal DAVIDSON ,  Eng Hun OOI ,  Yossi TSFATI ,  Ran SHIMON

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20230100670A1

公开(公告)日：2023-03-30

申请号：US17483880

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Alaa BEIDAS ,  Elan BANIN ,  Assaf BEN-BASSAT ,  Ofir DEGANI ,  Ashoke RAVI

IPC: G06N3/04 ,  G06N3/063

Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable oscillator configured to generate an oscillator signal. The spiking neuron may further include a circuit configured to obtain an integration value based on received input spike signals. The spiking neuron may further include a leakage circuit configured to obtain a leakage value based on the oscillator signal. The spiking neuron may further include an oscillator activator configured to activate or deactivate the triggerable oscillator based on the leakage value and the integration value.

公开(公告)号：US20220345338A1

公开(公告)日：2022-10-27

申请号：US17754311

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Elan BANIN ,  Rotem BANIN ,  Ofir DEGANI ,  Eytan MANN

IPC: H04L25/49

Abstract: An apparatus for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol is provided. The apparatus comprises an input interface configured to receive information about a bit value of the bit. Further, the apparatus comprises a transmission circuit configured to, if the bit value is a first value, transmit the plurality of payload data symbols at predetermined positions in a data signal as pulses of variable pulse length. The respective pulse length of each of the pulses is selected based on the symbol value of the payload data symbol represented by the respective pulse. If the bit value is a second value, the transmission circuit is configured to transmit a pulse exhibiting a pulse length being longer than a maximum payload data symbol pulse length defined in the communication protocol at the predetermined position of the pulse for the d-th payload data symbol of the plurality of payload data symbols, d=k+i if k+i≤z. d=([k+i] mod z) if k+i>z. k is the symbol value of the i-th payload data symbol of the plurality of payload data symbols, z is the number of possible symbol values of the payload data symbols defined in the communication protocol, and 1≤i≤z.

公开(公告)号：US20220278690A1

公开(公告)日：2022-09-01

申请号：US17355217

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Evgeny SHUMAKER ,  Elan BANIN ,  Ofir DEGANI ,  Gil HOROVITZ

IPC: H03L7/24 ,  H03L7/099 ,  H03L7/085 ,  G04F10/00

Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.

公开(公告)号：US20220200782A1

公开(公告)日：2022-06-23

申请号：US17481357

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Elan BANIN ,  Evgeny SHUMAKER ,  Ofir DEGANI ,  Rotem BANIN ,  Shahar GROSS

IPC: H04L7/033 ,  H04L27/22 ,  H04L27/152

Abstract: A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.

公开(公告)号：US20210199511A1

公开(公告)日：2021-07-01

申请号：US16727966

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Omer SHOLEV ,  Elan BANIN ,  Ofir DEGANI ,  Assaf BEN-BASSAT

IPC: G01K7/00 ,  H04B1/04

Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.

公开(公告)号：US20240223416A1

公开(公告)日：2024-07-04

申请号：US18147736

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Hossein ALAVI ,  Elan BANIN ,  Ofir DEGANI ,  Ashoke RAVI

IPC: H04L27/00 ,  H04L27/26

CPC classification number: H04L27/0014 ,  H04L27/2657 ,  H04L2027/0016 ,  H04L2027/0026

Abstract: A system includes a processor configured to determine a frequency offset between a first local oscillator and a second local oscillator using a combined radio signal received at a first transceiver circuit; wherein the combined radio signal comprises a first signal transmitted by the first transceiver circuit and a second signal transmitted by a second transceiver circuit.

公开(公告)号：US20230093115A1

公开(公告)日：2023-03-23

申请号：US17482480

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Assaf BEN-BASSAT ,  Elan BANIN ,  Alaa BEIDAS ,  Ofir DEGANI ,  Ashoke RAVI

IPC: G06N3/063 ,  G06N3/04 ,  H03K3/037

Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable and frequency-controllable oscillator that is configured to generate an oscillator signal. The spiking neuron may further include a spike signal detector that is configured to generate spike detection signals in response to detection of input spike signals. The spike signal detector may generate the spike detection signals based on the oscillator signal. The spiking neuron may further include a neuron structure that is configured to provide an output spike signal based on the spike detection signals and the oscillator signal.