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11.发明申请公开(公告)号：US20180217811A1
公开(公告)日：2018-08-02
申请号：US15422966
申请日：2017-02-02
Applicant: Intel Corporation
Inventor： Bogdan Pasca
Abstract: An integrated circuit may include normalization circuitry that can be used when converting a fixed-point number to a floating-point number. The normalization circuitry may include at least a floating-point generation circuit that receives the fixed-point number and that creates a corresponding floating-point number. The normalization circuitry may then leverage an embedded digital signal processing (DSP) block on the integrated circuit to perform an arithmetic operation by removing the leading one from the created floating-point number. The resulting number may have a fractional component and an exponent value, which can then be used to derive the final normalized value.
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公开(公告)号：US20230273770A1
公开(公告)日：2023-08-31
申请号：US18122656
申请日：2023-03-16
Applicant: Intel Corporation
Inventor： Sergey Vladimirovich Gribok , Martin Langhammer , Bogdan Pasca
Abstract: Integrated circuit devices, methods, and circuitry for implementing and using an iterative multiplicative modular reduction circuit are provided. Such circuitry may include polynomial multiplication circuitry and modular reduction circuitry that may operate concurrently. The polynomial multiplication circuitry may multiply a first input value to a second input value to compute a product. The modular reduction circuitry may perform modular reduction on a first component of the product while the polynomial multiplication circuitry is still generating other components of the product.
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公开(公告)号：US11301213B2
公开(公告)日：2022-04-12
申请号：US16450555
申请日：2019-06-24
Applicant: Intel Corporation
Inventor： Martin Langhammer , Bogdan Pasca
IPC: G06F7/544 , H03K19/177
Abstract: An integrated circuit with a large multiplier is provided. The multiplier may be configured to receive large input operands with thousands of bits. The multiplier may be implemented using a multiplier decomposition scheme that is recursively flattened into multiple decomposition levels to expose a tree of adders. The adders may be collapsed into a merged pipelined structure, where partial sums are forwarded from one level to the next while bypassing intervening prefix networks. The final correct sum is not calculated until later. In accordance with the decomposition technique, the partial sums are successively halved, which allows the prefix networks to be smaller from one level to the next. This allows all sums to be calculated at approximately the same pipeline depth, which significantly reduces latency with no or limited pipeline balancing.
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公开(公告)号：US11256978B2
公开(公告)日：2022-02-22
申请号：US15863544
申请日：2018-01-05
Applicant: Intel Corporation
Inventor： Bogdan Pasca , Martin Langhammer
Abstract: The present disclosure relates generally to techniques for enhancing recurrent neural networks (RNNs) implemented on an integrated circuit. In particular, approximations of activation functions used in an RNN, such as sigmoid and hyperbolic tangent, may be implemented in an integrated circuit, which may result in increased efficiencies, reduced latency, increased accuracy, and reduced resource consumption involved with implementing machine learning.
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公开(公告)号：US11003446B2
公开(公告)日：2021-05-11
申请号：US15842343
申请日：2017-12-14
Applicant: Intel Corporation
Inventor： Martin Langhammer , Gregg William Baeckler , Bogdan Pasca
Abstract: Adder trees may be constructed for efficient packing of arithmetic operators into an integrated circuit. The operands of the trees may be truncated to pack an integer number of nodes per logic array block. As a result, arithmetic operations may pack more efficiently onto the integrated circuit while providing increased precision and performance.
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Patent Agency Ranking
公开(公告)号：US20200004506A1
公开(公告)日：2020-01-02
申请号：US16566059
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： Martin Langhammer , Bogdan Pasca
Abstract: An integrated circuit may be provided with a modular multiplication circuit. The modular multiplication circuit may include an input multiplier for computing the product of two input signals, truncated multipliers for computing another product based on a modulus value and the product, a subtraction circuit for computing a difference between the two products. An error correction circuit may use the difference to look up an estimated quotient value and to subtract out an integer multiple of the modulus value from the difference in a single step, wherein the integer multiple is equal to the estimated quotient value. A final adjustment stage may be used to remove any remaining residual estimation error.
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17.发明公开公开(公告)号：US20240289168A1
公开(公告)日：2024-08-29
申请号：US18506687
申请日：2023-11-10
Applicant: Intel Corporation
Inventor： Krishnan Ananthanarayanan , Martin Langhammer , Om Ji Omer , Bogdan Pasca , Kamlesh Pillai , Pramod Udupa
IPC: G06F9/50
CPC classification number: G06F9/5027
Abstract: Systems, apparatuses and methods may provide for technology that identifies a type of a first activation function, identifies a derivative level of the first activation function, and generates a first instruction based on the type of the first activation function and the derivative level of the first activation function. The technology also includes an accelerator having logic coupled to one or more substrates, the logic including a compute engine including a plurality of arithmetic operators, a multiplexer network coupled to the compute engine, and a controller coupled to the multiplexer network, the controller to detect the first instruction, decode the first instruction to identify the first activation function, and drive the multiplexer network to form first connections between two or more of the plurality of arithmetic operators in accordance with the first activation function, wherein the first connections are to cause the compute engine to conduct the first activation function.
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公开(公告)号：US20230026331A1
公开(公告)日：2023-01-26
申请号：US17952085
申请日：2022-09-23
Applicant: Intel Corporation
Inventor： Sergey Gribok , Bogdan Pasca , Martin Langhammer
Abstract: A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.
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公开(公告)号：US20220188072A1
公开(公告)日：2022-06-16
申请号：US17560838
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Martin Langhammer , Bogdan Pasca
Abstract: This disclosure is directed to multiplier circuitry that includes a multiplier that is configurable to generate a plurality of subproducts by performing a plurality of multiplication operations involving values having a first precision using a recursive multiplication process in which a second multiplier of the multiplier performs a second plurality of multiplication operations involving values having a second precision that are derived from the values having the first precision.
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公开(公告)号：US20220107783A1
公开(公告)日：2022-04-07
申请号：US17552436
申请日：2021-12-16
Applicant: Intel Corporation
Inventor： Martin Langhammer , Bogdan Pasca , Sergey Gribok , Gregg William Baeckler , Andrei Hagiescu
Abstract: A programmable device may be configured to support machine learning training operations using matrix multiplication circuitry. In some embodiments, the multiplication is implemented on a systolic array. The systolic array includes an array of processing elements, each of which includes hybrid floating-point dot-product circuitry.
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