公开(公告)号：US20210125897A1

公开(公告)日：2021-04-29

申请号：US16665621

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Krishna Vasanth VALAVALA ,  Ravindranath V. MAHAJAN ,  Chandra Mohan JHA

IPC: H01L23/38 ,  H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments include a semiconductor package with a thermoelectric cooler (TEC), a method to form such semiconductor package, and a semiconductor packaged system. The semiconductor package includes a die with a plurality of backend layers on a package substrate. The backend layers couple the die to the package substrate. The semiconductor package includes the TEC in the backend layers of the die. The TEC includes a plurality of N-type layers, a plurality of P-type layers, and first and second conductive layers. The first conductive layer is directly coupled to outer regions of bottom surfaces of the N-type and P-type layers, and the second conductive layer is directly coupled to inner regions of top surfaces of the N-type and P-type layers. The first conductive layer has a width greater than a width of the second conductive layer. The N-type and P-type layers are directly disposed between the first and second conductive layers.

公开(公告)号：US20210104484A1

公开(公告)日：2021-04-08

申请号：US16596338

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Chandra Mohan JHA ,  Prasad RAMANATHAN ,  Xavier F. BRUN ,  Jimmin YAO ,  Mark ALLEN

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L23/373

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

公开(公告)号：US20210104448A1

公开(公告)日：2021-04-08

申请号：US16596377

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Feras EID ,  Chandra Mohan JHA ,  Je-Young CHANG

IPC: H01L23/367 ,  H01L23/427 ,  H01L23/373 ,  H05K7/20

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a lateral heat spreader (LHS) over a package substrate, and a first die over the LHS and package substrate. The first die has a first region and a second region, where the first and second regions are on a bottom surface of the first die. The semiconductor package includes a plurality of second dies over the first die, and an integrated heat spreader (IHS) over the second dies, first die, LHS, and package substrate. The IHS includes a lid and legs. The LHS thermally couples the first region of the first die to the legs of the IHS, and laterally extends from below the first region of the first die to below the legs of the IHS. The LHS may be comprised of graphene sheets, heat pipes, or vapor chambers and coupled to a thermal conductive material and a sealant.