公开(公告)号：US20210391244A1

公开(公告)日：2021-12-16

申请号：US16898196

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Chandra Mohan JHA ,  Pooya TADAYON ,  Aastha UPPAL ,  Weihua TANG ,  Paul DIGLIO ,  Xavier BRUN

IPC: H01L23/498 ,  H01L23/373 ,  H01L23/522 ,  H01L21/56 ,  H01L21/78

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US20210249324A1

公开(公告)日：2021-08-12

申请号：US16783819

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chia-Pin CHIU ,  Chandra Mohan JHA

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

公开(公告)号：US20210193547A1

公开(公告)日：2021-06-24

申请号：US16721802

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chandra Mohan JHA ,  Je-Young CHANG ,  Chia-Pin CHIU ,  Liwei WANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

公开(公告)号：US20230140685A1

公开(公告)日：2023-05-04

申请号：US18089537

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihua TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC: H01L23/42 ,  H01L23/522 ,  H01L23/373 ,  H01L23/367

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20170179000A1

公开(公告)日：2017-06-22

申请号：US14975247

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Chandra Mohan JHA ,  Kelly Porter LOFGREEN

IPC: H01L23/38 ,  H01L35/34 ,  H01L23/367 ,  H01L35/08 ,  H01L35/32

CPC classification number: H01L23/38 ,  H01L23/3675 ,  H01L35/08 ,  H01L35/32 ,  H01L35/34 ,  H01L2224/16225 ,  H01L2224/73253

Abstract: Thermoelectric coolers having solderless electrical interconnects, and semiconductor packages incorporating such thermoelectric coolers, are described. In an example, a thermoelectric cooler includes a solderless electrode electrically connecting a P-type semiconductor column to an N-type semiconductor column, and the solderless electrode is in direct contact with diffusion barrier layers separating the solderless electrode from the P-type and N-type semiconductor material layers of the semiconductor columns. Methods of manufacturing thermoelectric coolers having solderless electrical interconnects are also described.

公开(公告)号：US20240234245A1

公开(公告)日：2024-07-11

申请号：US18612949

申请日：2024-03-21

Applicant: Intel Corporation

Inventor： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihua TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/522 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/49575 ,  H01L23/5384 ,  H01L24/20 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20210118756A1

公开(公告)日：2021-04-22

申请号：US16659395

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chandra Mohan JHA ,  Je-Young CHANG ,  Chia-Pin CHIU

IPC: H01L23/15 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.

公开(公告)号：US20210028087A1

公开(公告)日：2021-01-28

申请号：US16522443

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihau TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20210280497A1

公开(公告)日：2021-09-09

申请号：US16810341

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Xavier F. BRUN ,  Chandra Mohan JHA

IPC: H01L23/473 ,  H01L25/065 ,  H01L23/053

Abstract: A modular technique for die-level liquid cooling is described. In an example, an integrated circuit assembly includes a first silicon die comprising a device side and a backside opposite the device side. The integrated circuit assembly also includes a second silicon die comprising a plurality of fluidly accessible channels therein. A dielectric interface directly couples the second silicon die to a backside of the first silicon die.

公开(公告)号：US20210193549A1

公开(公告)日：2021-06-24

申请号：US16721122

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Feras EID ,  Chandra Mohan JHA ,  Je-Young CHANG

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages and thermal solutions for such electronic packages. In an embodiment, an electronic package comprises, a package substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface connecting the first surface to the second surface. In an embodiment, the electronic package further comprises a heat spreader, where a first portion of the heat spreader is attached to the first surface of the package substrate and a second portion of the heat spreader is attached to the second surface of the package substrate. In an embodiment, a third portion of the heat spreader adjacent to the sidewall surface of the package substrate connects the first portion of the heat spreader to the second portion of the heat spreader.