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公开(公告)号：US11949446B2
公开(公告)日：2024-04-02
申请号：US16912741
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Daniel Gruber , Mark Elzinga , Martin Clara
CPC classification number: H04B1/582 , H01Q1/246 , H01Q23/00 , H04B1/0475 , H04B2001/0433
Abstract: The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.
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公开(公告)号：US11528182B2
公开(公告)日：2022-12-13
申请号：US17351288
申请日：2021-06-18
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Christian Lindholm , Hundo Shin
Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
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公开(公告)号：US11038516B1
公开(公告)日：2021-06-15
申请号：US16886817
申请日：2020-05-29
Applicant: Intel Corporation
Inventor： Kameran Azadet , Ramon Sanchez , Albert Molina , Martin Clara , Daniel Gruber , Matteo Camponeschi
Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.
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14.发明授权公开(公告)号：US12074606B2
公开(公告)日：2024-08-27
申请号：US17131811
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Christian Lindholm , Martin Clara , Giacomo Cascio
IPC: H03M1/08 , H03K19/003 , H03K19/0185 , H04B1/12
CPC classification number: H03M1/0827 , H03K19/00384 , H03K19/018578 , H04B1/12
Abstract: A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.
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公开(公告)号：US12034452B2
公开(公告)日：2024-07-09
申请号：US17132000
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Michael Kalcher , Martin Clara
Abstract: A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.
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Patent Agency Ranking
公开(公告)号：US11489536B1
公开(公告)日：2022-11-01
申请号：US17358093
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Martin Clara , Daniel Gruber , Giacomo Cascio , Albert Molina
Abstract: Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.
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公开(公告)号：US11183993B2
公开(公告)日：2021-11-23
申请号：US16724564
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Hundo Shin , Kameran Azadet , Martin Clara , Daniel Gruber
Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.
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公开(公告)号：US20210194747A1
公开(公告)日：2021-06-24
申请号：US16724458
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Kameran Azadet , Martin Clara , Daniel Gruber , Christian Lindholm , Hundo Shin
Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
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公开(公告)号：US10965308B1
公开(公告)日：2021-03-30
申请号：US16912792
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Daniel Gruber , Martin Clara , Michael Kalcher
Abstract: A digital-to-analog converter comprises a plurality of first digital-to-analog converter cells configured to generate a first analog signal based on first digital data, wherein the first digital-to-analog converter cells of the plurality of first digital-to-analog converter cells are coupled to a first output node for coupling to a first load. Further, the digital-to-analog converter comprises a plurality of second digital-to-analog converter cells configured to generate one or more second analog signals based on second digital data, wherein the second digital-to-analog converter cells of the plurality of second digital-to-analog converter cells are coupled to one or more second output nodes, and wherein the plurality of first digital-to-analog converter cells and the plurality of second digital-to-analog converter cells are coupled to a power supply node for coupling to a mutual power supply.
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20.发明授权公开(公告)号：US12113500B2
公开(公告)日：2024-10-08
申请号：US17131809
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , L Mark Elzinga , Martin Clara , Giacomo Cascio
CPC classification number: H03H11/24 , H04B1/1607 , H04W88/08
Abstract: An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals.
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