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    Analog-to-digital converter system, transceiver, base station and mobile device
    3.
    发明授权
    Analog-to-digital converter system, transceiver, base station and mobile device 有权

    公开(公告)号：US11528182B2

    公开(公告)日：2022-12-13

    申请号：US17351288

    申请日：2021-06-18

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

    IPC: H03M1/10 ,  H04L27/36 ,  H03M1/06 ,  H04B1/04

    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

    Analog-to-digital converter
    4.
    发明授权
    Analog-to-digital converter 有权

    公开(公告)号：US11277146B2

    公开(公告)日：2022-03-15

    申请号：US16912733

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Christian Lindholm ,  Hundo Shin ,  Martin Clara

    IPC: H03M1/34 ,  H03M1/68 ,  H03M1/38 ,  H03M1/12 ,  H03M1/00 ,  H03M1/10 ,  H03M1/06

    Abstract: An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

    Apparatus for generating a plurality of phase-shifted clock signals, electronic system, base station and mobile device
    5.
    发明授权
    Apparatus for generating a plurality of phase-shifted clock signals, electronic system, base station and mobile device 有权

    公开(公告)号：US11183993B2

    公开(公告)日：2021-11-23

    申请号：US16724564

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Hundo Shin ,  Kameran Azadet ,  Martin Clara ,  Daniel Gruber

    IPC: H03H11/16 ,  H03K5/13 ,  H03K5/00 ,  H04W88/02 ,  H04W88/08

    Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

    ANALOG-TO-DIGITAL CONVERTER SYSTEM, TRANSCEIVER, BASE STATION AND MOBILE DEVICE
    6.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER SYSTEM, TRANSCEIVER, BASE STATION AND MOBILE DEVICE 有权

    公开(公告)号：US20210194747A1

    公开(公告)日：2021-06-24

    申请号：US16724458

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

    IPC: H04L27/36 ,  H03M1/10 ,  H03M1/06

    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

    Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device
    7.
    发明授权
    Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device 有权

    公开(公告)号：US12028090B2

    公开(公告)日：2024-07-02

    申请号：US17754310

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet ,  Martin Clara ,  Hundo Shin

    IPC: H03M1/66 ,  H03M1/80

    CPC classification number: H03M1/808

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

    Digital-to-analog converter, data processing system, base station, and mobile device
    8.
    发明授权
    Digital-to-analog converter, data processing system, base station, and mobile device 有权

    公开(公告)号：US11901908B2

    公开(公告)日：2024-02-13

    申请号：US17754148

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Kameran Azadet ,  Yu-Shan Wang ,  Hundo Shin ,  Martin Clara

    IPC: H04B1/04 ,  H03M1/06 ,  H04B1/10

    CPC classification number: H03M1/0614 ,  H04B1/0475 ,  H04B1/1018

    Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

    Apparatus for generating synchronized clock signals, elec-tronic system, base station and mobile device
    9.
    发明授权
    Apparatus for generating synchronized clock signals, elec-tronic system, base station and mobile device 有权

    公开(公告)号：US11378999B2

    公开(公告)日：2022-07-05

    申请号：US16724486

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Yu-Shan Wang ,  Martin Clara ,  Daniel Gruber ,  Hundo Shin ,  Kameran Azadet

    IPC: G06F1/12 ,  G06F1/14 ,  G06F1/08

    Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.

    Analog-to-digital converter
    10.
    发明申请
    Analog-to-digital converter 有权

    公开(公告)号：US20210409035A1

    公开(公告)日：2021-12-30

    申请号：US16912733

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Christian Lindholm ,  Hundo Shin ,  Martin Clara

    IPC: H03M1/68 ,  H03M1/38

    Abstract: An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

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