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    Analog-to-digital converter system, transceiver, base station and mobile device
    1.
    发明授权
    Analog-to-digital converter system, transceiver, base station and mobile device 有权

    公开(公告)号：US11528182B2

    公开(公告)日：2022-12-13

    申请号：US17351288

    申请日：2021-06-18

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

    IPC: H03M1/10 ,  H04L27/36 ,  H03M1/06 ,  H04B1/04

    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

    Time-interleaved analog-to-digital converter system
    5.
    发明授权
    Time-interleaved analog-to-digital converter system 有权

    公开(公告)号：US11271578B2

    公开(公告)日：2022-03-08

    申请号：US17059495

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet ,  Matteo Camponeschi ,  Jose Luis Ceballos ,  Christian Lindholm

    IPC: H03M1/12 ,  H03M1/06 ,  H03M1/10

    Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

    Apparatus and method for time-interleaved analog-to-digital conversion
    6.
    发明授权
    Apparatus and method for time-interleaved analog-to-digital conversion 有权

    公开(公告)号：US11082054B1

    公开(公告)日：2021-08-03

    申请号：US16912812

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Giacomo Cascio ,  Christian Lindholm ,  Albert Molina ,  Martin Clara

    IPC: H03M1/12 ,  H03M1/06 ,  H03M1/36

    Abstract: The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.

    Reference buffer circuit, analog-to-digital converter system, receiver, base station and mobile device
    8.
    发明授权
    Reference buffer circuit, analog-to-digital converter system, receiver, base station and mobile device 有权

    公开(公告)号：US12074606B2

    公开(公告)日：2024-08-27

    申请号：US17131811

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Christian Lindholm ,  Martin Clara ,  Giacomo Cascio

    IPC: H03M1/08 ,  H03K19/003 ,  H03K19/0185 ,  H04B1/12

    CPC classification number: H03M1/0827 ,  H03K19/00384 ,  H03K19/018578 ,  H04B1/12

    Abstract: A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

    Analog-to-digital converter
    10.
    发明授权
    Analog-to-digital converter 有权

    公开(公告)号：US11277146B2

    公开(公告)日：2022-03-15

    申请号：US16912733

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Christian Lindholm ,  Hundo Shin ,  Martin Clara

    IPC: H03M1/34 ,  H03M1/68 ,  H03M1/38 ,  H03M1/12 ,  H03M1/00 ,  H03M1/10 ,  H03M1/06

    Abstract: An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

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