公开(公告)号：US20240396568A1

公开(公告)日：2024-11-28

申请号：US18792714

申请日：2024-08-02

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Brent Carlton

IPC: H03M1/14 ,  G06F7/544 ,  H03M1/18

Abstract: Systems, apparatuses and methods may provide for technology including a digital to analog conversion (DAC) stage to generate analog input activation signals, a multiply-accumulate (MAC) computation stage coupled to the DAC stage, the MAC computation stage to generate output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage, an analog integration stage coupled to the MAC computation stage, the analog integration stage to conduct partial sum accumulations on the output activation results, and analog to digital conversion (ADC) stage coupled to the analog integration stage, the ADC stage to generate digital computation results based on an output of the analog integration stage, and a controller to vary a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.

公开(公告)号：US20240113725A1

公开(公告)日：2024-04-04

申请号：US18539957

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: H03M1/46 ,  G11C7/16

CPC classification number: H03M1/466 ,  G11C7/16 ,  H03M1/462

Abstract: Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.

公开(公告)号：US20220366968A1

公开(公告)日：2022-11-17

申请号：US17816442

申请日：2022-08-01

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G06F7/544

Abstract: Technology for generating an SRAM-based in-memory computing macro includes replacing a SRAM cell cluster defined by a generic SRAM macro with a single-bit multi-bank cluster, the single-bit multi-bank cluster including a plurality of CiM SRAM cells and a plurality of C-2C capacitor ladder cells, arranging a plurality of single-bit multi-bank clusters to form a multi-bit multi-bank cluster, and arranging a plurality of multi-bit multi-bank clusters into a multi-dimensional MAC computational unit within a region of the generic SRAM macro, where an output of at least two of the multi-bit multi-bank clusters are electrically coupled to form an output analog activation line, and where a plurality of bit lines and a plurality of word lines remain at the same grid locations as provided in the generic SRAM macro. Embodiments include arranging a plurality of multi-dimensional MAC computational units into an in-memory MAC computing array.

公开(公告)号：US20220222518A1

公开(公告)日：2022-07-14

申请号：US17709796

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Kuilin Clark Chen

IPC: G06N3/063 ,  G06V10/774 ,  G06F7/544

Abstract: Dynamic compensation of analog circuitry impairments in ANNs is provided. An example ANN includes an analog circuitry that performs MAC operations based on weights. To compensate analog circuitry impairments, a signal package including a training signal and an input signal, is formed. The training signal is fed into the ANN. The ANN generates an output signal through MAC operations by the analog circuitry with the training signal and the weights. The output signal is compared with a reference signal to determine an error in the output signal. The reference signal may include one or more ground-truth classifications of the training signal. The error is used to compute a compensation coefficient, which compensates impact of analog circuitry impairments on accuracy in outputs of the ANN. The ANN is updated with the compensation coefficient. The analog circuitry performs MAC operations with the input signal, the compensation coefficient, and the set of weights.

公开(公告)号：US12154638B2

公开(公告)日：2024-11-26

申请号：US17353493

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Renzhi Liu ,  Deepak Dasalukunte

IPC: G11C27/02 ,  G06N3/063

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

公开(公告)号：US20230251943A1

公开(公告)日：2023-08-10

申请号：US18298906

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Renzhi Liu ,  Hechen Wang ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F11/20

CPC classification number: G06F11/2041

Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

公开(公告)号：US20220334801A1

公开(公告)日：2022-10-20

申请号：US17855097

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Shigeki Tomishima

IPC: G06F7/523 ,  G06F7/50

Abstract: Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.

公开(公告)号：US20220138548A1

公开(公告)日：2022-05-05

申请号：US17578324

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Niranjan Mylarappa Gowda ,  Andrey Belogolovy

IPC: G06N3/063 ,  G06V10/82 ,  G06V10/764 ,  G06V10/94

Abstract: An analog neural network including a hardware activation function is provided. A layer of the analog neural network includes a sequence of processing elements that receives analog signals, perform MAC operations on the analog signals, and generates analog outputs. The analog outputs are provided to an analog circuitry that can apply an activation function on the analog outputs. The output of the analog circuitry are also analog signals, which can further be provided to the next layer in the network. The analog circuitry may include a differential pair of transistors to compute the tan h activation function. Alternatively, the analog circuitry may include a comparator and multiplexer to compute the ReLU activation function. Compared with digital implementation of activation functions, the analog circuitry eliminates the need of converting the analog outputs of the layer to digital signals and the need of converting the result of the activation function to analog signals.

公开(公告)号：US20220012016A1

公开(公告)日：2022-01-13

申请号：US17485179

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte

IPC: G06F7/544 ,  G06F7/523 ,  G06N3/04 ,  H03M1/78 ,  H03M1/80

Abstract: Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.