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    ANALOG HARDWARE IMPLEMENTATION OF ACTIVATION FUNCTIONS
    1.
    发明申请
    ANALOG HARDWARE IMPLEMENTATION OF ACTIVATION FUNCTIONS 有权

    公开(公告)号：US20220138548A1

    公开(公告)日：2022-05-05

    申请号：US17578324

    申请日：2022-01-18

    Applicant: Intel Corporation

    Inventor： Hechen Wang ,  Niranjan Mylarappa Gowda ,  Andrey Belogolovy

    IPC: G06N3/063 ,  G06V10/82 ,  G06V10/764 ,  G06V10/94

    Abstract: An analog neural network including a hardware activation function is provided. A layer of the analog neural network includes a sequence of processing elements that receives analog signals, perform MAC operations on the analog signals, and generates analog outputs. The analog outputs are provided to an analog circuitry that can apply an activation function on the analog outputs. The output of the analog circuitry are also analog signals, which can further be provided to the next layer in the network. The analog circuitry may include a differential pair of transistors to compute the tan h activation function. Alternatively, the analog circuitry may include a comparator and multiplexer to compute the ReLU activation function. Compared with digital implementation of activation functions, the analog circuitry eliminates the need of converting the analog outputs of the layer to digital signals and the need of converting the result of the activation function to analog signals.

    STYLUS TRAJECTORY PREDICTION
    2.
    发明申请
    STYLUS TRAJECTORY PREDICTION 有权

    公开(公告)号：US20250004577A1

    公开(公告)日：2025-01-02

    申请号：US18216217

    申请日：2023-06-29

    Applicant: Intel Corporation

    Inventor： Niranjan Mylarappa Gowda ,  Antonio S. Cheng ,  Andrey Belogolovy ,  Evgeny Stupachenko

    IPC: G06F3/0354

    Abstract: System and techniques for predicting a stylus position while interacting on a surface are described herein. The prediction begins by obtaining a set of points that are derived from a stylus moving on a surface. An artificial neural network (ANN) may be invoked on an input set. Here, the input set is based on the set of points from the stylus. The ANN is configured to output a next point from the input set, and the ANN is trained to minimize angular error for the next point over other errors. Once the next point is provided by the ANN, the next point may be communicated for rendering on a display.

    TRANSMISSION LATENCY REDUCTION
    3.
    发明申请
    TRANSMISSION LATENCY REDUCTION 审中-公开

    公开(公告)号：US20200036644A1

    公开(公告)日：2020-01-30

    申请号：US16370475

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Andrey Belogolovy ,  Jeffrey Boyd ,  Hao Ruan ,  Longcheng Zhu

    IPC: H04L12/825 ,  H04L12/801 ,  H04L12/891 ,  H04L12/841 ,  H04L12/835 ,  H04L1/00

    Abstract: Systems and methods of reducing transmission time are described. Uniform-sized original packets are generated from a data frame having a payload with an identifier and data. The packets include the identifier, total block number, block index that specifies an order of the packet, and the data. The packets are encoded to form redundant packets with the identifier, block number, block index and redundant data. The available block index for the original and redundant packets are different. The packets are transmitted by individual modems over different channels at transmission rates that are each configured to minimize free space in an input buffer of the modem and are dependent on feedback from the receiver. The feedback indicates a difference between the transmission rate and a reception rate. The encoding rate is dependent on the original packets over the original and redundant packets or a maximum transmission rate over the remaining transmission rates.

    Techniques to perform forward error correction for an electrical backplane
    4.
    发明授权
    Techniques to perform forward error correction for an electrical backplane 有权
    对电气背板进行前向纠错的技术

    公开(公告)号：US09544089B2

    公开(公告)日：2017-01-10

    申请号：US14698102

    申请日：2015-04-28

    Applicant: Intel Corporation

    Inventor： Ilango S. Ganga ,  Luke Chang ,  Andrey Belogolovy ,  Ovchinnikov Andrei

    IPC: H03M13/00 ,  H04L1/00 ,  H03M13/33 ,  H04L7/04 ,  G06F11/10 ,  H04L7/033

    CPC classification number: H04L1/0043 ,  G06F11/10 ,  H03M13/33 ,  H03M13/63 ,  H03M13/6312 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0047 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0072 ,  H04L7/041 ,  Y02D30/32

    Abstract: A media independent interface and circuitry of a forward error correction (FEC) sublayer are provided, the circuitry of the FEC sublayer to perform forward error correction, the FEC sublayer coupled to a physical coding sublayer and a physical medium attachment (PMA) sublayer. The FEC sublayer include an encoder having a reverse gearbox, a compressor coupled to said reverse gearbox, a selector coupled to said compressor, a parity generator coupled to said compressor, a multiplexer coupled to said compressor, selector and said parity generator, a scrambler coupled to said multiplexer, and a pseudo-noise generator coupled to said scrambler.

    Abstract translation: 提供了前向纠错（FEC）子层的媒体独立接口和电路，FEC子层的电路执行前向纠错，FEC子层耦合到物理编码子层和物理介质附着（PMA）子层。 FEC子层包括具有倒档齿轮箱的编码器，耦合到所述倒档齿轮箱的压缩机，耦合到所述压缩器的选择器，耦合到所述压缩器的奇偶校验发生器，耦合到所述压缩器，选择器和所述奇偶校验发生器的多路复用器， 到所述多路复用器，以及耦合到所述加扰器的伪噪声发生器。

    POWER HARVESTING
    7.
    发明申请
    POWER HARVESTING 有权

    公开(公告)号：US20170181110A1

    公开(公告)日：2017-06-22

    申请号：US14971167

    申请日：2015-12-16

    Applicant: INTEL CORPORATION

    Inventor： Andrey Belogolovy

    IPC: H04W52/54

    CPC classification number: H04W52/58 ,  H02J7/02 ,  H02J7/025 ,  H04L5/0055 ,  H04W4/80 ,  H04W72/0406 ,  H04W72/0473 ,  H04W72/048

    Abstract: Techniques for forming a wireless RF power harvesting and data network are described. An example electronic device includes an antenna array, a processor, and instructions to direct the actions of the processor. The instructions control the processor to perform a registration process for a power harvesting device. The registration process is to obtain information that enables the transmission of a targeted power packet to the power harvesting device through beamforming. The instructions also direct the processor transmit the targeted power packet to the power harvesting device.

    METHOD, APPARATUS AND SYSTEM OF MANAGING AN ENCODER OUTPUT RATE BASED UPON WIRELESS COMMUNICATION LINK FEEDBACK
    10.
    发明申请
    METHOD, APPARATUS AND SYSTEM OF MANAGING AN ENCODER OUTPUT RATE BASED UPON WIRELESS COMMUNICATION LINK FEEDBACK 审中-公开
    基于无线通信链路反馈管理编码器输出速率的方法，装置和系统

    公开(公告)号：US20160309366A1

    公开(公告)日：2016-10-20

    申请号：US15130989

    申请日：2016-04-17

    Applicant: INTEL CORPORATION

    Inventor： Guoqing Li ,  Mikhail S. Tsvetkov ,  Andrey Belogolovy ,  Vallabhajosyula S. Somayazulu ,  Lei Shen

    IPC: H04W28/16 ,  H04L12/24

    CPC classification number: H04W28/16 ,  H04L1/0009 ,  H04L1/0014 ,  H04L41/12 ,  H04L43/0811 ,  H04L45/42 ,  H04W28/10

    Abstract: Machine-readable media, methods, apparatus and system for managing an encoder output rate at least partially based upon wireless communication link feedback are described. In some embodiments, a device driver of the system may generate link information indicating quality of a wireless communication link between the system and another system, wherein the link information is generated at least partially based upon at least one of media access layer (MAC) information and physical layer information of the system. A system managing entity of the system may manage an output rate of an encoder of the system at least partially based upon the link information.

    Abstract translation: 描述了至少部分地基于无线通信链路反馈来管理编码器输出速率的机器可读介质，方法，装置和系统。 在一些实施例中，系统的设备驱动器可以生成指示系统与另一系统之间的无线通信链路的质量的链接信息，其中至少部分地基于媒体接入层（MAC）信息中的至少一个生成链路信息 和系统的物理层信息。 系统的系统管理实体可以至少部分地基于链接信息来管理系统的编码器的输出速率。

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