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公开(公告)号：US11012409B2
公开(公告)日：2021-05-18
申请号：US15942031
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Liuyang Lily Yang , Huaxin Li , Li Zhao , Marcio Juliato , Shabbir Ahmed , Manoj R. Sastry
Abstract: There is disclosed in one example a computing apparatus, including: a hardware platform; a network interface to communicatively couple to a bus lacking native support for authentication; and an anomaly detection engine to operate on the hardware platform and configured to: receive a first data stream across a first time; symbolize and approximate the first data stream, including computing a first window sum; receive a second data stream across a second time substantially equal in length to the first time, the second data stream including data across the plurality of dimensions from the first data stream; symbolize and approximate the second data stream, including computing a second window sum; compute a difference between the first window sum and the second window sum; determine that difference exceeds a threshold and that the correlation across the plurality of dimensions is broken; and flag a potential anomaly.
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公开(公告)号：US10741098B2
公开(公告)日：2020-08-11
申请号：US15716170
申请日：2017-09-26
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Li Zhao , Manoj R. Sastry
Abstract: One embodiment provides an apparatus. The apparatus includes a lightweight cryptographic engine (LCE), the LCE is optimized and has an associated throughput greater than or equal to a target throughput.
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公开(公告)号：US10355891B2
公开(公告)日：2019-07-16
申请号：US15720389
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Marcio Juliato , Li Zhao , Ahmed Shabbir , Manoj R. Sastry , Santosh Ghosh , Rafael Misoczki
Abstract: Embodiments may include systems and methods for authenticating a message between a transmitter and a receiver. An apparatus for communication may include a transmitter to transmit a message to a receiver via a physical channel coupling the transmitter and the receiver. The message may be transmitted via a plurality of transmission voltage levels varied from a plurality of nominal voltage levels on the physical channel. The transmitter may include a voltage generator to generate the plurality of transmission voltage levels varied in accordance with a sequence of voltage variations from the plurality of nominal voltage levels for the message. The sequence of voltage variations may serve to authenticate the message between the transmitter and the receiver. Other embodiments may be described and/or claimed.
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公开(公告)号：US10348495B2
公开(公告)日：2019-07-09
申请号：US15441030
申请日：2017-02-23
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Rafael Misoczki , Manoj R. Sastry , Li Zhao
Abstract: Apparatuses and methods associated with configurable crypto hardware engine are disclosed herein. In embodiments, an apparatus for signing or verifying a message may comprise: a hardware hashing computation block to perform hashing computations; a hardware hash chain computation block to perform successive hash chain computations; a hardware private key generator to generate private keys; and a hardware public key generator to generate public keys, including signature generations and signature verifications. The hardware hashing computation block, the hardware hash chain computation block, the hardware private key generator, and the hardware public key generator may be coupled to each other and selectively cooperate with each other to perform private key generation, public key generation, signature generation or signature verification at different points in time. Other embodiments may be disclosed or claimed.
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公开(公告)号：US10341116B2
公开(公告)日：2019-07-02
申请号：US15392266
申请日：2016-12-28
Applicant: Intel Corporation
Inventor： Xiruo Liu , Rafael Misoczki , Manoj R Sastry , Santosh Ghosh , Li Zhao
Abstract: An attestation protocol between a prover device (P), a verifier device (V), and a trusted third-party device (TTP). P and TTP have a first trust relationship represented by a first cryptographic representation based on a one-or-few-times, hash-based, signature key. V sends an attestation request to P, with the attestation request including a second cryptographic representation of a second trust relationship between V and TTP. In response to the attestation request, P sends a validation request to TTP, with the validation request being based on a cryptographic association of the first trust relationship and the second trust relationship. TTP provides a validation response including a cryptographic representation of verification of validity of the first trust relationship and the second trust relationship. P sends an attestation response to V based on the validation response.
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Patent Agency Ranking
公开(公告)号：US10326587B2
公开(公告)日：2019-06-18
申请号：US15392252
申请日：2016-12-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Li Zhao , Rafael Misoczki , Manoj R Sastry
IPC: H04L9/06 , H04L9/32 , G06F13/28 , G06F21/72 , G06F1/3296
Abstract: A cryptography accelerator system includes a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and an on-the-fly hashing circuit to hash data read from a first memory circuit on-the-fly before writing the read data to a second memory circuit. The hashing circuit performs at least one of integrity protection and firmware/software (FW/SW) verification of the data prior to writing the data to the second memory circuit. The on-the-fly hashing circuit includes a bit repositioning circuit to designate an order of bits of a binary word in a register from a most significant bit (MSB) to a least significant bit (LSB) for performing computations without rotating bits in the register, and an on-the-fly round constant generator circuit to generate a round constant from a counter.
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公开(公告)号：US20180241554A1
公开(公告)日：2018-08-23
申请号：US15441030
申请日：2017-02-23
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Rafael Misoczki , Manoj R. Sastry , Li Zhao
CPC classification number: H04L9/0861 , H04L9/002 , H04L9/0643 , H04L9/3236 , H04L9/3247 , H04L2209/12 , H04L2209/38
Abstract: Apparatuses and methods associated with configurable crypto hardware engine are disclosed herein. In embodiments, an apparatus for signing or verifying a message may comprise: a hardware hashing computation block to perform hashing computations; a hardware hash chain computation block to perform successive hash chain computations; a hardware private key generator to generate private keys; and a hardware public key generator to generate public keys, including signature generations and signature verifications. The hardware hashing computation block, the hardware hash chain computation block, the hardware private key generator, and the hardware public key generator may be coupled to each other and selectively cooperate with each other to perform private key generation, public key generation, signature generation or signature verification at different points in time. Other embodiments may be disclosed or claimed.
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公开(公告)号：US20180198709A1
公开(公告)日：2018-07-12
申请号：US15859301
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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公开(公告)号：US20180183573A1
公开(公告)日：2018-06-28
申请号：US15392252
申请日：2016-12-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Li Zhao , Rafael Misoczki , Manoj R. Sastry
CPC classification number: H04L9/0618 , G06F1/3296 , G06F13/28 , G06F21/72 , H04L9/0643 , H04L9/3242 , Y02D10/14
Abstract: A cryptography accelerator system includes a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and an on-the-fly hashing circuit to hash data read from a first memory circuit on-the-fly before writing the read data to a second memory circuit. The hashing circuit performs at least one of integrity protection and firmware/software (FW/SW) verification of the data prior to writing the data to the second memory circuit. The on-the-fly hashing circuit includes a bit repositioning circuit to designate an order of bits of a binary word in a register from a most significant bit (MSB) to a least significant bit (LSB) for performing computations without rotating bits in the register, and an on-the-fly round constant generator circuit to generate a round constant from a counter.
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公开(公告)号：US09773432B2
公开(公告)日：2017-09-26
申请号：US14752873
申请日：2015-06-27
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Li Zhao , Manoj R. Sastry
CPC classification number: G09C1/00 , H04L9/0631 , H04L2209/122
Abstract: One embodiment provides an apparatus. The apparatus includes a lightweight cryptographic engine (LCE), the LCE is optimized and has an associated throughput greater than or equal to a target throughput.
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