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公开(公告)号：US10817176B2
公开(公告)日：2020-10-27
申请号：US16011280
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Ian F. Adams , John Keys , Michael P. Mesnier , Dave Minturn
Abstract: Embodiments of the present disclosure may relate to a compute offload controller that may include a parser to parse a received compute offload command, and identify a block-based compute descriptor based at least in part on the compute offload command. In some embodiments, the compute offload controller may further include an offload executor to perform an operation on data in a block-based storage device based at least in part on the block-based compute descriptor. In some embodiments, the block-based compute descriptor may include a virtual input object, a virtual output object, and a compute type identifier. Other embodiments may be described and/or claimed.
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公开(公告)号：US20200328973A1
公开(公告)日：2020-10-15
申请号：US16870991
申请日：2020-05-10
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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公开(公告)号：US11238203B2
公开(公告)日：2022-02-01
申请号：US15640448
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Rameshkumar Illikkal , Ananth Sankaranarayanan , David Zimmerman , Pratik M. Marolia , Suchit Subhaschandra , Dave Minturn
IPC: G06F30/331 , G06F21/76 , G06F3/06 , G06F9/445 , G06F12/0817 , G06F21/79 , G06F30/34
Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.
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公开(公告)号：US09485178B2
公开(公告)日：2016-11-01
申请号：US14229545
申请日：2014-03-28
Applicant: Intel Corporation
Inventor： Srihari Makikeni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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Patent Agency Ranking
公开(公告)号：US20190042093A1
公开(公告)日：2019-02-07
申请号：US16011280
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Ian F. Adams , John Keys , Michael P. Mesnier , Dave Minturn
IPC: G06F3/06
Abstract: Embodiments of the present disclosure may relate to a compute offload controller that may include a parser to parse a received compute offload command, and identify a block-based compute descriptor based at least in part on the compute offload command. In some embodiments, the compute offload controller may further include an offload executor to perform an operation on data in a block-based storage device based at least in part on the block-based compute descriptor. In some embodiments, the block-based compute descriptor may include a virtual input object, a virtual output object, and a compute type identifier. Other embodiments may be described and/or claimed.
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公开(公告)号：US20190005176A1
公开(公告)日：2019-01-03
申请号：US15640448
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Rameshkumar Illikkal , Ananth Sankaranarayanan , David Zimmerman , Pratik M. Marolia , Suchit Subhaschandra , Dave Minturn
Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.
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公开(公告)号：US20180198709A1
公开(公告)日：2018-07-12
申请号：US15859301
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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公开(公告)号：US10652147B2
公开(公告)日：2020-05-12
申请号：US15859301
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06 , H04L12/931
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
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公开(公告)号：US20170048142A1
公开(公告)日：2017-02-16
申请号：US15339354
申请日：2016-10-31
Applicant: Intel Corporation
Inventor： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC: H04L12/741 , H04L29/06
CPC classification number: H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
Abstract translation: 一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段 协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。 该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷 。 该方法还包括产生导致因特网协议分组的接收处理的信号。
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