公开(公告)号：US09685213B2

公开(公告)日：2017-06-20

申请号：US15347736

申请日：2016-11-09

Applicant: Intel Corporation

Inventor： Dany-Sebastien Ly-Gagnon ,  Kiran Pangal ,  Raymond W. Zeng ,  Mase J. Taub

IPC: G11C11/00 ,  G11C13/00 ,  H01L29/06

CPC classification number: G11C11/00 ,  G06F11/1048 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L29/06 ,  H04L65/403

Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.

公开(公告)号：US20160372194A1

公开(公告)日：2016-12-22

申请号：US14742316

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Dany-Sebastien Ly-Gagnon ,  Kiran Pangal ,  Raymond W. Zeng ,  Mase J. Taub

IPC: G11C13/00

CPC classification number: G11C11/00 ,  G06F11/1048 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L29/06 ,  H04L65/403

Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。