公开(公告)号：US20240022248A1

公开(公告)日：2024-01-18

申请号：US18028513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Stefano PELLERANO ,  Christopher HULL ,  Todor MLADENOV ,  JongSeok PARK ,  Ilya KLOCHKOV ,  Sushil SUBRAMANIAN

IPC: H03K17/92 ,  H03F3/21 ,  H03M1/66 ,  G06N10/40

CPC classification number: H03K17/92 ,  H03F3/21 ,  H03M1/66 ,  G06N10/40

Abstract: Apparatus and methods for interfacing an integrated qubit control chip and a solid state qubit; detecting a qubit state with a transition pulse histogram; high resolution and high speed rectangular pulse generation; large-scale spin qubit state readout; and activity-based clock control.

公开(公告)号：US20220200750A1

公开(公告)日：2022-06-23

申请号：US17124536

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Peter SAGAZIO ,  Chun C. LEE ,  Stefano PELLERANO ,  Christopher D. HULL

IPC: H04L5/00 ,  H04W72/08 ,  H04W72/04

Abstract: Various aspects of this disclosure provide a receiver. The receiver may include a down-converter configured to down-convert a received communication signal at a predefined carrier frequency, with a reference signal received from a reference signal generator, and a processor configured to perform a signal quality detection to identify a signal quality metric of the received communication signal at the predefined carrier frequency, and to provide a frequency adjusting signal to the reference signal generator to change the frequency of the reference signal based on the performed signal quality detection to identify the signal quality metric of the received communication signal at the predefined carrier frequency.