公开(公告)号：US20220093647A1

公开(公告)日：2022-03-24

申请号：US17030226

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20210408283A1

公开(公告)日：2021-12-30

申请号：US16912127

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Ashish AGRAWAL ,  Anand S. MURTHY ,  Cory BOMBERGER ,  Jack T. KAVALIEROS ,  Koustav GANGULY ,  Ryan KEECH ,  Siddharth CHOUKSEY ,  Susmita GHOSE ,  Willy RACHMADY

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/165

Abstract: Gate-all-around integrated circuit structures having strained source or drain structures on an insulator layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on an insulator layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is on the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. Each of the pair of epitaxial source or drain structures has a compressed or an expanded lattice.