公开(公告)号：US20230317786A1

公开(公告)日：2023-10-05

申请号：US17700215

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Varun MISHRA ,  Tahir GHANI ,  Pratik PATEL ,  Wonil CHUNG ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

公开(公告)号：US20240284652A1

公开(公告)日：2024-08-22

申请号：US18644874

申请日：2024-04-24

Applicant: Intel Corporation

Inventor： Peng ZHENG ,  Varun MISHRA ,  Tahir GHANI

IPC: H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US20240088254A1

公开(公告)日：2024-03-14

申请号：US18514995

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh MEHANDRU ,  Cory WEBER ,  Willy RACHMADY ,  Varun MISHRA

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/0217 ,  H01L21/02293 ,  H01L21/02532 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1091 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20220216221A1

公开(公告)日：2022-07-07

申请号：US17701419

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Peng ZHENG ,  Varun MISHRA ,  Tahir GHANI

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/36 ,  H01L29/167 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/265

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US20220093647A1

公开(公告)日：2022-03-24

申请号：US17030226

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20240164080A1

公开(公告)日：2024-05-16

申请号：US18375858

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Peng ZHENG ,  Varun MISHRA ,  Harold W. KENNEL ,  Eric A. KARL ,  Tahir GHANI

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/10

CPC classification number: H10B10/12 ,  H01L29/0669 ,  H01L29/1037

Abstract: Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.

公开(公告)号：US20240153956A1

公开(公告)日：2024-05-09

申请号：US18409519

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20220246743A1

公开(公告)日：2022-08-04

申请号：US17727603

申请日：2022-04-22

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Cory WEBER ,  Willy RACHMADY ,  Varun MISHRA

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20210305388A1

公开(公告)日：2021-09-30

申请号：US16833184

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Cory WEBER ,  Willy RACHMADY ,  Varun MISHRA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20210296323A1

公开(公告)日：2021-09-23

申请号：US16827570

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Peng ZHENG ,  Varun MISHRA ,  Tahir GHANI

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/36 ,  H01L29/167 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.