公开(公告)号：US20230082276A1

公开(公告)日：2023-03-16

申请号：US17988612

申请日：2022-11-16

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Susmita GHOSE ,  Siddharth CHOUKSEY

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/32 ,  H01L29/165 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20250142870A1

公开(公告)日：2025-05-01

申请号：US19004029

申请日：2024-12-27

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H10D30/62 ,  H10D30/01 ,  H10D62/822

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20250048698A1

公开(公告)日：2025-02-06

申请号：US18922831

申请日：2024-10-22

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Mark T. BOHR ,  Tahir GHANI ,  Biswajeet GUHA

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

公开(公告)号：US20240186378A1

公开(公告)日：2024-06-06

申请号：US18440526

申请日：2024-02-13

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Susmita GHOSE ,  Siddharth CHOUKSEY

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/32 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/167 ,  H01L29/32 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/0276 ,  H01L21/30625 ,  H01L22/26

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20230317789A1

公开(公告)日：2023-10-05

申请号：US17710841

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Anand S. MURTHY ,  Cory BOMBERGER ,  Subrina RAFIQUE ,  Chi-Hing CHOI ,  Mohammad HASAN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/41783

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with selective silicide contacts thereon are described. In an example, an integrated circuit structure includes a plurality of stacks of nanowires. A plurality of epitaxial source or drain structures is around ends of corresponding ones of the stacks of nanowires. A silicide layer is on an entirety of a top surface of the plurality of epitaxial source or drain structures. A conductive trench contact is on the silicide layer. A dielectric layer is vertically intervening between a portion of the conductive trench contact and the silicide layer.

公开(公告)号：US20230058558A1

公开(公告)日：2023-02-23

申请号：US17982459

申请日：2022-11-07

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Mark T. BOHR ,  Tahir GHANI ,  Biswajeet GUHA

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

公开(公告)号：US20230043665A1

公开(公告)日：2023-02-09

申请号：US17968558

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Stephen CEA ,  Biswajeet GUHA ,  Anupama BOWONDER ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L29/267

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US20230197785A1

公开(公告)日：2023-06-22

申请号：US18110315

申请日：2023-02-15

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Suresh VISHWANATH

IPC: H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L23/00 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/0649 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

公开(公告)号：US20210167210A1

公开(公告)日：2021-06-03

申请号：US16700826

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20200312981A1

公开(公告)日：2020-10-01

申请号：US16370449

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Susmita GHOSE ,  Zachary GEIGER

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.