公开(公告)号：US10790895B2

公开(公告)日：2020-09-29

申请号：US16025814

申请日：2018-07-02

Applicant: INTEL IP CORPORATION

Inventor： Assaf Kasher ,  Michael Genossar

IPC: H04B7/06 ,  H04B7/0413

Abstract: Various embodiments may be generally directed to antenna array weight vector selection techniques for 60 GHz multiple-input multiple-output (MIMO) communications. In some embodiments, using one or more such techniques, a 60 GHz-capable transmitting device may select respective antenna array weight vectors for two or more transmit antenna arrays, and a 60 GHz-capable receiving device may select respective antenna array weight vectors for two or more receive antenna arrays. In various embodiments, in order to obtain information for use in selecting such antenna array weight vectors, the transmitter and receiver may utilize one or more existing beamforming training algorithms defined for 60 GHz single-input single-output (SISO) communications. In some embodiments, for example, the transmitter and receiver may utilize one or more beamforming training algorithms defined in IEEE 802.11ad-2012. The embodiments are not limited in this context.

公开(公告)号：US10721761B2

公开(公告)日：2020-07-21

申请号：US16239202

申请日：2019-01-03

Applicant: Intel IP Corporation

Inventor： Laurent Cariou ,  Carlos Cordeiro ,  Chittabrata Ghosh ,  Assaf Kasher ,  Solomon B. Trainin

IPC: H04W72/04 ,  H04W72/12 ,  H04W74/04 ,  H04W74/08

Abstract: Computer readable media, methods, and apparatuses for centralized channel access for primary and secondary channels are disclosed. An apparatus is disclosed comprising memory and processing circuitry. The processing circuitry is configured to encode a schedule of one or more resource allocations, wherein each resource allocation comprises a type of allocation, a bandwidth, an indication of a channel, a source association identification (AID), a destination AID, an allocation start, and a duration. The type of allocation may be a service period (SP) or a contention-based access period (CBAP). The channel may be an indication of a basic service set (BSS) or a personal BSS (PBSS) primary channel, BSS or PBSS secondary channel, or BSS or PBSS tertiary channel. The processing circuitry may be configured to transmit the schedule to one or more stations identified by the source AID and the destination AID of the one or more resource allocations.

公开(公告)号：US10531381B2

公开(公告)日：2020-01-07

申请号：US15969330

申请日：2018-05-02

Applicant: Intel IP Corporation

Inventor： Solomon B. Trainin ,  Assaf Kasher ,  Carlos Cordeiro ,  Laurent Cariou

IPC: H04W52/02 ,  H04W74/08 ,  H04W84/12

Abstract: Devices and methods of limiting wideband STA communication are generally described. The STA receives, over a primary channel, a wakeup frame containing an indication of a SP or CBAP to acquire a wideband TXOP over a wide bandwidth channel including the primary channel and a secondary channel and a control trailer having an indication of the wide bandwidth channel. Prior to the SP/CBAP, the STA opens reception from the primary channel to the wide bandwidth channel. The STA then communicates with another STA over the wide bandwidth channel and subsequently reduces reception from the wide bandwidth channel to the primary channel. The wakeup frame originates from an AP/PCP or the other STA, and contains fields indicating the wakeup frame length and SP or a sensing time length prior to the CBAP.

公开(公告)号：US10439694B2

公开(公告)日：2019-10-08

申请号：US15870060

申请日：2018-01-12

Applicant: Intel IP Corporation

Inventor： Assaf Kasher ,  Carlos Cordeiro ,  Alexander Alexandrovich Maltsev ,  Artyom Lomayev

IPC: H04L12/40 ,  H04B7/06 ,  H04B7/0413 ,  H04L29/06

Abstract: Apparatus, computer readable media, and methods for enhanced beamforming training in a wireless local area network are disclosed. An apparatus of a access point or station is disclosed. The apparatus including processing circuitry where the processing circuitry is configured to encode an EBRP packet comprising a first portion comprising an indication of a first number of transmit antenna training settings (N-TX), and an indication of a second number of receive training subfields per N-TX settings (N-RX), and a second portion comprising a third number of training subfields. The third number may be less than or equal to N-TX times N-RX. The processing circuitry may be configured to cause the first portion of the EBRP packet to be transmitted and cause the second portion to be transmitted, where two or more of the third number of training subfields are to be transmitted simultaneously using different antennas and orthogonal sequences.

公开(公告)号：US10313051B2

公开(公告)日：2019-06-04

申请号：US15832201

申请日：2017-12-05

Applicant: Intel IP Corporation

Inventor： Maxim Greenberg ,  Assaf Kasher ,  Michael Genossar ,  Igor Gutman

IPC: H04L1/00 ,  H04L27/20 ,  H04L27/34 ,  H04W72/04 ,  H04L27/00

Abstract: This disclosure describes methods, apparatus, and systems related to a modulation and coding scheme (MCS) system. The device may determine a wireless communications channel with a first device in accordance with a wireless communications standard. The device may generate a header in accordance with a communication standard, the header including, at least in part, a modulation and coding scheme (MCS) index value. The device may determine a code rate associated with the MCS index value based at least in part on the wireless communications channel. The device may cause to send the header to the first device over the wireless communications channel based at least in part on the MCS index value.

公开(公告)号：US20190159239A1

公开(公告)日：2019-05-23

申请号：US16239202

申请日：2019-01-03

Applicant: Intel IP Corporation

Inventor： Laurent Cariou ,  Carlos Cordeiro ,  Chittabrata Ghosh ,  Assaf Kasher ,  Solomon B. Trainin

IPC: H04W72/12 ,  H04W72/04 ,  H04W74/04 ,  H04W74/08

CPC classification number: H04W72/1289 ,  H04W72/042 ,  H04W72/0446 ,  H04W72/0453 ,  H04W72/048 ,  H04W74/04 ,  H04W74/0891

Abstract: Computer readable media, methods, and apparatuses for centralized channel access for primary and secondary channels are disclosed. An apparatus is disclosed comprising memory and processing circuitry. The processing circuitry is configured to encode a schedule of one or more resource allocations, wherein each resource allocation comprises a type of allocation, a bandwidth, an indication of a channel, a source association identification (AID), a destination AID, an allocation start, and a duration. The type of allocation may be a service period (SP) or a contention-based access period (CBAP). The channel may be an indication of a basic service set (BSS) or a personal BSS (PBSS) primary channel, BSS or PBSS secondary channel, or BSS or PBSS tertiary channel. The processing circuitry may be configured to transmit the schedule to one or more stations identified by the source AID and the destination AID of the one or more resource allocations.

公开(公告)号：US10219286B2

公开(公告)日：2019-02-26

申请号：US15889561

申请日：2018-02-06

Applicant: Intel IP Corporation

Inventor： Laurent Cariou ,  Chittabrata Ghosh ,  Carlos Cordeiro ,  Assaf Kasher

IPC: H04W72/12

Abstract: Embodiments of a station (STA) and method for communication on primary and secondary channel resources are generally described herein. The STA may transmit a grant frame to indicate a transmission of a data payload by the STA during a grant period. The grant frame may indicate whether the data payload is to be transmitted on primary channel resources or on secondary channel resources. The STA may transmit the data payload to a destination STA on the secondary channel resources when the grant frame indicates that the data payload is to be transmitted on the secondary channel resources. The grant frame may be transmitted on the primary channel resources and on the secondary channel resources when the grant frame indicates that the data payload is to be transmitted on the secondary channel resources.

公开(公告)号：US10172164B2

公开(公告)日：2019-01-01

申请号：US15282340

申请日：2016-09-30

Applicant: Intel IP Corporation

Inventor： Laurent Cariou ,  Solomon B. Trainin ,  Ou Yang ,  Assaf Kasher

IPC: H04W74/00 ,  H04W84/12 ,  H04L12/26 ,  H04L5/00 ,  H04W74/08 ,  H04B17/336 ,  H04B7/0413

Abstract: Computing readable media, apparatuses, and methods for spatial reuse with training in RTS-CTS are disclosed. An apparatus comprising processing circuitry is disclosed. The processing circuitry configured to: decode a received frame, the frame including either a request to send (RTS) frame or a clear to send (CTS) frame, with an initial portion of the frame indicating a plurality of training fields (TRN-R) at an end of the frame. The processing circuitry further configured to perform a clear channel assessment (CCA) for each receive (Rx) sector of a plurality of Rx sectors using the plurality of TRN-Rs.

公开(公告)号：US20180287732A1

公开(公告)日：2018-10-04

申请号：US15832201

申请日：2017-12-05

Applicant: Intel IP Corporation

Inventor： Maxim Greenberg ,  Assaf Kasher ,  Michael Genossar ,  Igor Gutman

IPC: H04L1/00 ,  H04L27/20 ,  H04L27/00 ,  H04L27/34 ,  H04W72/04

CPC classification number: H04L1/0009 ,  H04L1/0003 ,  H04L1/0025 ,  H04L1/0057 ,  H04L1/0075 ,  H04L27/0008 ,  H04L27/2078 ,  H04L27/34 ,  H04W72/04

Abstract: This disclosure describes methods, apparatus, and systems related to a modulation and coding scheme (MCS) system. The device may determine a wireless communications channel with a first device in accordance with a wireless communications standard. The device may generate a header in accordance with a communication standard, the header including, at least in part, a modulation and coding scheme (MCS) index value. The device may determine a code rate associated with the MCS index value based at least in part on the wireless communications channel. The device may cause to send the header to the first device over the wireless communications channel based at least in part on the MCS index value.

公开(公告)号：US10075323B2

公开(公告)日：2018-09-11

申请号：US14757816

申请日：2015-12-26

Applicant: Intel IP Corporation

Inventor： Assaf Kasher ,  Michael Genossar ,  Maxim Greenberg ,  Vladimir Kravtsov

IPC: H04L27/36 ,  H04L5/00 ,  H04L27/26

CPC classification number: H04L27/361 ,  H04L1/00 ,  H04L5/0053 ,  H04L27/2605 ,  H04L27/2636

Abstract: This disclosure describes methods, devices, and systems related to interleaving and deinterleaving symbols used in single carrier modulation and coding schemes. A device is disclosed comprising at least one memory storing computer-executable instructions, and at least one processor configured to access the at least one memory. The at least one processor is further configured to execute the computer-executable instructions to: receive a source data bit string from the at least one memory, scramble the source data bit string, parse the scrambled source data bit string into a plurality of segments, assign a portion of the plurality of segments to a Single Carrier-Block (SC-BLK), and encode the portion of the plurality of segments into a code word, wherein the code word comprises a plurality of bit groups, and each bit group comprises one or more bits. The at least one processor is further configured to determine a number of modulation symbols based at least in part on group size; map each of the plurality of bit groups to a corresponding modulation symbol; group the modulation symbols into an interleaved symbol block associated with the SC-BLK; group the plurality of modulation symbols in the interleaved symbol block into a second code word that corresponds to the first code word; and transmit a packet comprising the interleaved symbol block.