公开(公告)号：US20110278674A1

公开(公告)日：2011-11-17

申请号：US13192561

申请日：2011-07-28

申请人： Terence Blackwell Hook ,  Jeffrey Bowman Johnson ,  James Spiros Nakos

发明人： Terence Blackwell Hook ,  Jeffrey Bowman Johnson ,  James Spiros Nakos

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/82 ,  H01L21/823878 ,  H01L21/823892

摘要： Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.

摘要翻译： 沟槽隔离结构和形成沟槽隔离结构的方法。 所述结构包括在衬底的硅区域中的沟槽，所述沟槽从所述衬底的顶表面延伸到所述硅区域中; 在沟槽的侧壁上的离子注入停止层; 填充沟槽中的剩余空间的介电填充材料，所述介电填充材料不包括在所述停止层中发现的任何材料; 在所述沟槽的第一侧上的所述硅区域的第一区域中的N型掺杂剂物质; 所述N型掺杂剂物质在所述电介质材料的与所述沟槽的第一侧相邻的第一区域中; 在沟槽的第二侧上的硅区域的第二区域中的P型掺杂物种; 以及邻近沟槽第二侧的电介质材料的第二区域中的P型掺杂剂物质。

公开(公告)号：US08012848B2

公开(公告)日：2011-09-06

申请号：US11839585

申请日：2007-08-16

申请人： Terence Blackwell Hook ,  Jeffrey Bowman Johnson ,  James Spiros Nakos

发明人： Terence Blackwell Hook ,  Jeffrey Bowman Johnson ,  James Spiros Nakos

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/82 ,  H01L21/823878 ,  H01L21/823892

摘要： Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.

摘要翻译： 沟槽隔离结构和形成沟槽隔离结构的方法。 所述结构包括在衬底的硅区域中的沟槽，所述沟槽从所述衬底的顶表面延伸到所述硅区域中; 在沟槽的侧壁上的离子注入停止层; 填充沟槽中的剩余空间的介电填充材料，所述介电填充材料不包括在所述停止层中发现的任何材料; 在所述沟槽的第一侧上的所述硅区域的第一区域中的N型掺杂剂物质; 所述N型掺杂剂物质在所述电介质材料的与所述沟槽的第一侧相邻的第一区域中; 在沟槽的第二侧上的硅区域的第二区域中的P型掺杂物种; 以及邻近沟槽第二侧的电介质材料的第二区域中的P型掺杂剂物质。

公开(公告)号：US06522304B2

公开(公告)日：2003-02-18

申请号：US09832557

申请日：2001-04-11

申请人： Arne Watson Ballantine ,  Daniel Charles Edelstein ,  James Spiros Nakos ,  Anthony Kendall Stamper

发明人： Arne Watson Ballantine ,  Daniel Charles Edelstein ,  James Spiros Nakos ,  Anthony Kendall Stamper

IPC分类号： H01Q1300

CPC分类号： H01Q13/0283

摘要： An integrated horn antenna device with an integrated circuit (IC) chip including a metallic horn structure having a wide aperture, a horizontal waveguide with a tapered via that electromagnetically communicates with a vertical waveguide structure to transmit energy to and from an electronic sub-component transceiver device forming part of the IC chip. Another embodiment of the invention comprises a plurality of multiple discrete IC chips having the integrated horn antenna devices incorporated therewith forming a module for data transmissions between these IC chips. Another embodiment of the invention includes additional external waveguide structures such as optical fibers external to the chips, where radiation is aligned between the horn structures and these waveguides. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.

公开(公告)号：US06215190B1

公开(公告)日：2001-04-10

申请号：US09076525

申请日：1998-05-12

申请人： James Allen Bruce ,  Jonathan Daniel Chapple-Sokol ,  Charles W. Koburger, III ,  Michael James Lercel ,  Randy William Mann ,  James Spiros Nakos ,  John Joseph Prxarik ,  Kirk David Peterson ,  Jed Hickory Rankin

发明人： James Allen Bruce ,  Jonathan Daniel Chapple-Sokol ,  Charles W. Koburger, III ,  Michael James Lercel ,  Randy William Mann ,  James Spiros Nakos ,  John Joseph Prxarik ,  Kirk David Peterson ,  Jed Hickory Rankin

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888 ,  H01L27/11

摘要： A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

摘要翻译： 通过采用双重绝缘薄膜叠层作为掩模，提供了一种无边界的相对于栅极导体的扩散接触，用于限定整个芯片的栅极导体形状，并在限定栅极导体形状之后在暴露的导电层上提供相对较薄的损伤防止层 。 在一个实施例中，通过在衬底上形成绝缘层来提供无边界接触，在绝缘层上提供导电层，在导电层上提供第二绝缘层，在第二绝缘层上提供第三绝缘层，去除预选 第二绝缘层和第三绝缘层的部分，在去除第二和第三绝缘层的那些区域中提供防损害层，去除第三绝缘层的预选部分，去除损坏防止层，去除导电层的暴露部分 并且去除第二绝缘层的现在暴露部分。

公开(公告)号：US06187679B1

公开(公告)日：2001-02-13

申请号：US08807739

申请日：1997-02-26

申请人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC分类号： H01L2144

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.

摘要翻译： 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

公开(公告)号：US5828131A

公开(公告)日：1998-10-27

申请号：US586046

申请日：1996-01-16

申请人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC分类号： C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.

摘要翻译： 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。

公开(公告)号：US07897939B2

公开(公告)日：2011-03-01

申请号：US12167271

申请日：2008-07-03

申请人： Alan Michael Chandler ,  Tushar Desai ,  Ellis Craig Hayford ,  Nicholas Mone, Jr. ,  James Spiros Nakos

发明人： Alan Michael Chandler ,  Tushar Desai ,  Ellis Craig Hayford ,  Nicholas Mone, Jr. ,  James Spiros Nakos

IPC分类号： G21K5/00

CPC分类号： H01J37/3171 ,  H01J37/16 ,  H01J2237/0213 ,  H01J2237/022 ,  H01J2237/0268

摘要： A method of improving the performance of charged beam apparatus. The method including: providing the apparatus, the apparatus comprising: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; and a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and positioning one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.

摘要翻译： 一种提高带电束装置性能的方法。 该方法包括：提供该装置，该装置包括：具有内表面的腔室; 用于抽空室的泵口; 腔室内的衬底保持器; 以及室内的带电粒子束，由源产生的带电束和带电粒子束撞击衬底; 并且将一个或多个衬垫定位成与腔室的内表面的一个或多个不同区域接触，衬垫防止由带电束和衬底的相互作用产生的材料涂覆在腔室的内表面的一个或多个不同区域 房间。

公开(公告)号：US20090045468A1

公开(公告)日：2009-02-19

申请号：US11839585

申请日：2007-08-16

申请人： Terence Blackwell Hook ,  Jeffrey Bowman Johnson ,  James Spiros Nakos

发明人： Terence Blackwell Hook ,  Jeffrey Bowman Johnson ,  James Spiros Nakos

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/82 ,  H01L21/823878 ,  H01L21/823892

摘要： Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.

摘要翻译： 沟槽隔离结构和形成沟槽隔离结构的方法。 所述结构包括在衬底的硅区域中的沟槽，所述沟槽从所述衬底的顶表面延伸到所述硅区域中; 在沟槽的侧壁上的离子注入停止层; 填充沟槽中的剩余空间的介电填充材料，所述介电填充材料不包括在所述停止层中发现的任何材料; 在所述沟槽的第一侧上的所述硅区域的第一区域中的N型掺杂剂物质; 所述N型掺杂剂物质在所述电介质材料的与所述沟槽的第一侧相邻的第一区域中; 在沟槽的第二侧上的硅区域的第二区域中的P型掺杂物种; 以及邻近沟槽第二侧的电介质材料的第二区域中的P型掺杂剂物质。

公开(公告)号：US06498096B2

公开(公告)日：2002-12-24

申请号：US09800911

申请日：2001-03-08

申请人： James Allan Bruce ,  Jonathan Daniel Chapple-Sokol ,  Charles W. Koburger, III ,  Michael James Lercel ,  Randy William Mann ,  James Spiros Nakos ,  John Joseph Pekarik ,  Kirk David Peterson ,  Jed Hickory Rankin

发明人： James Allan Bruce ,  Jonathan Daniel Chapple-Sokol ,  Charles W. Koburger, III ,  Michael James Lercel ,  Randy William Mann ,  James Spiros Nakos ,  John Joseph Pekarik ,  Kirk David Peterson ,  Jed Hickory Rankin

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888 ,  H01L27/11

摘要： A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

摘要翻译： 通过采用双重绝缘薄膜叠层作为掩模，提供了一种无边界的相对于栅极导体的扩散接触，用于限定整个芯片的栅极导体形状，并在限定栅极导体形状之后在暴露的导电层上提供相对较薄的损伤防止层 。 在一个实施例中，通过在衬底上形成绝缘层来提供无边界接触，在绝缘层上提供导电层，在导电层上提供第二绝缘层，在第二绝缘层上提供第三绝缘层，去除预选 第二绝缘层和第三绝缘层的部分，在去除第二和第三绝缘层的那些区域中提供防损害层，去除第三绝缘层的预选部分，去除损坏防止层，去除导电层的暴露部分 并且去除第二绝缘层的现在暴露部分。

公开(公告)号：US07897940B2

公开(公告)日：2011-03-01

申请号：US12168168

申请日：2008-07-07

申请人： Alan Michael Chandler ,  Tushar Desai ,  Ellis Craig Hayford ,  Nicholas Mone, Jr. ,  James Spiros Nakos

发明人： Alan Michael Chandler ,  Tushar Desai ,  Ellis Craig Hayford ,  Nicholas Mone, Jr. ,  James Spiros Nakos

IPC分类号： G01K5/00

CPC分类号： H01J37/3171 ,  H01J37/16 ,  H01J2237/0213 ,  H01J2237/022 ,  H01J2237/0268

摘要： An apparatus. The apparatus including: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.

摘要翻译： 一种装置 该装置包括：具有内表面的室; 用于抽空室的泵口; 腔室内的衬底保持器; 室内的带电粒子束，由源产生的带电束和带电粒子束撞击衬底; 以及与室的内表面的一个或多个不同区域接触的一个或多个衬垫，衬垫防止由带电束和衬底的相互作用产生的材料涂覆室的内表面的一个或多个不同区域 。