Apparatus for supplying voltage free from noise and method of operation the same
    11.
    发明申请
    Apparatus for supplying voltage free from noise and method of operation the same 失效
    用于提供无噪声电压的装置及其操作方法

    公开(公告)号:US20070285142A1

    公开(公告)日:2007-12-13

    申请号:US11647486

    申请日:2006-12-29

    IPC分类号: H03K3/356

    摘要: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

    摘要翻译: 电压供给装置包括电源噪声检测单元,电压选择单元,第一电源电压单元和第二电源电压单元。 功率噪声感测单元感测来自第一和第二功率的噪声,并输出功率噪声感测信号。 电压选择单元响应于电压供应使能信号和功率噪声感测信号输出第一和第二驱动信号。 第一电源电压单元响应于第一和第二驱动信号施加第一功率的电压。 第二电源电压单元响应于第一和第二驱动信号施加第二功率的电压。

    Method of manufacturing a CMOS transistor
    12.
    发明授权
    Method of manufacturing a CMOS transistor 失效
    制造CMOS晶体管的方法

    公开(公告)号:US06300184B1

    公开(公告)日:2001-10-09

    申请号:US09609158

    申请日:2000-06-30

    IPC分类号: H01L218238

    CPC分类号: H01L21/823842

    摘要: There is disclosed a method of manufacturing a CMOS transistor, by which ion implantation process is selectively performed to the gate formed region of a polysilicon film after a NMOS transistor region and a PMOS transistor region are defined in the process of manufacturing a CMOS transistor. Thus, it can obtain a reliable device by solving the problem occurring when polysilicon films doped with different impurities are simultaneously etched and the problem that a tungsten film is oxidized due to a selective oxidization process after forming a tungsten gate electrode.

    摘要翻译: 公开了一种制造CMOS晶体管的方法,在制造CMOS晶体管的过程中限定了NMOS晶体管区域和PMOS晶体管区域之后,通过其选择性地对多晶硅膜的栅极形成区域进行离子注入工艺。 因此,通过解决在同时蚀刻掺杂有不同杂质的多晶硅膜和在形成钨栅电极之后由于选择性氧化工艺而氧化钨膜的问题,可以获得可靠的器件。

    APPARATUS FOR SUPPLYING VOLTAGE FREE NOISE AND METHOD OF OPERATION THE SAME
    13.
    发明申请
    APPARATUS FOR SUPPLYING VOLTAGE FREE NOISE AND METHOD OF OPERATION THE SAME 失效
    用于提供无电压噪声的装置及其操作方法

    公开(公告)号:US20110266877A1

    公开(公告)日:2011-11-03

    申请号:US13180584

    申请日:2011-07-12

    IPC分类号: H02J4/00

    摘要: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

    摘要翻译: 电压供给装置包括电源噪声检测单元,电压选择单元,第一电源电压单元和第二电源电压单元。 功率噪声感测单元感测来自第一和第二功率的噪声,并输出功率噪声感测信号。 电压选择单元响应于电压供应使能信号和功率噪声感测信号输出第一和第二驱动信号。 第一电源电压单元响应于第一和第二驱动信号施加第一功率的电压。 第二电源电压单元响应于第一和第二驱动信号施加第二功率的电压。

    Circuit providing compensated power for sense amplifier and driving method thereof
    14.
    发明授权
    Circuit providing compensated power for sense amplifier and driving method thereof 有权
    用于读出放大器的电路提供补偿功率及其驱动方法

    公开(公告)号:US07825733B2

    公开(公告)日:2010-11-02

    申请号:US12136196

    申请日:2008-06-10

    申请人: Jun Gi Choi

    发明人: Jun Gi Choi

    IPC分类号: H03L7/099

    摘要: The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

    摘要翻译: 本发明公开了一种提供用于感测放大器的电源的电路,其通过补偿当读出放大器以选择性地产生的解耦噪声工作时在电源电压中产生的噪声来稳定提供给读出放大器的电源电压。 提供用于读出放大器的电源的电路包括感测放大电路,以感测和放大加载在具有第一功率的位线上的数据。 供电单元向感测放大电路提供第一功率。 解耦单元产生具有第二功率的去耦噪声,并将解耦噪声提供给第一电源电压。 解耦噪声保持包括感测放大电路的操作的时间点和之后的预定时间的周期。

    Method and apparatus for detecting semiconductor characterist variations
    15.
    发明授权
    Method and apparatus for detecting semiconductor characterist variations 有权
    用于检测半导体特征变化的方法和装置

    公开(公告)号:US07053672B2

    公开(公告)日:2006-05-30

    申请号:US10878444

    申请日:2004-06-28

    申请人: Jun Gi Choi

    发明人: Jun Gi Choi

    IPC分类号: H03K5/22

    CPC分类号: G01R31/2621 G01R31/2628

    摘要: The present invention discloses a skew detection device which can detect a skew of a transistor changed due to a driving voltage, a size and a process variable. The skew detection device includes a first potential level generator for outputting a first voltage, a second potential level generator for outputting a second voltage, a first level shifter for receiving the first voltage and outputting a first shift voltage, a second level shifter for receiving the second voltage and outputting a second shift voltage, and a comparator for comparing the first shift voltage with the second shift voltage. The first voltage is determined according to a drain-source current of a first MOS transistor operated in a linear region, and the second voltage is determined according to a drain-source current of a second MOS transistor operated in a saturation region.

    摘要翻译: 本发明公开了一种可以检测由于驱动电压,尺寸和过程变量而改变的晶体管的偏斜的偏斜检测装置。 偏斜检测装置包括用于输出第一电压的第一电位电平发生器,用于输出第二电压的第二电位电平发生器,用于接收第一电压并输出第一移位电压的第一电平移位器,用于接收第一电压的第二电平移位器 第二电压并输出第二移位电压;以及比较器,用于将第一移位电压与第二移位电压进行比较。 根据在线性区域中工作的第一MOS晶体管的漏 - 源电流来确定第一电压,并且根据在饱和区域中操作的第二MOS晶体管的漏 - 源电流来确定第二电压。

    Skew detection device
    16.
    发明申请
    Skew detection device 有权
    偏斜检测装置

    公开(公告)号:US20050206430A1

    公开(公告)日:2005-09-22

    申请号:US10878444

    申请日:2004-06-28

    申请人: Jun Gi Choi

    发明人: Jun Gi Choi

    IPC分类号: G11C8/00 G01R31/26 H03L5/00

    CPC分类号: G01R31/2621 G01R31/2628

    摘要: The present invention discloses a skew detection device which can detect a skew of a transistor changed due to a driving voltage, a size and a process variable. The skew detection device includes a first potential level generator for outputting a first voltage, a second potential level generator for outputting a second voltage, a first level shifter for receiving the first voltage and outputting a first shift voltage, a second level shifter for receiving the second voltage and outputting a second shift voltage, and a comparator for comparing the first shift voltage with the second shift voltage. The first voltage is determined according to a drain-source current of a first MOS transistor operated in a linear region, and the second voltage is determined according to a drain-source current of a second MOS transistor operated in a saturation region.

    摘要翻译: 本发明公开了一种可以检测由于驱动电压,尺寸和过程变量而改变的晶体管的偏斜的偏斜检测装置。 偏斜检测装置包括用于输出第一电压的第一电位电平发生器,用于输出第二电压的第二电位电平发生器,用于接收第一电压并输出第一移位电压的第一电平移位器,用于接收第一电压的第二电平移位器 第二电压并输出第二移位电压;以及比较器,用于将第一移位电压与第二移位电压进行比较。 根据在线性区域中工作的第一MOS晶体管的漏 - 源电流来确定第一电压,并且根据在饱和区域中操作的第二MOS晶体管的漏 - 源电流来确定第二电压。

    Internal voltage generating apparatus for a semiconductor memory device
    17.
    发明授权
    Internal voltage generating apparatus for a semiconductor memory device 有权
    一种用于半导体存储器件的内部电压产生装置

    公开(公告)号:US06751134B2

    公开(公告)日:2004-06-15

    申请号:US10330887

    申请日:2002-12-27

    IPC分类号: G11C700

    摘要: An internal voltage generating apparatus for a semiconductor memory device is described herein. The internal voltage generating apparatus is configured to execute an internal voltage margin test with a small number of pads by installing a forcing pad and fuse (or switch) in an initial reference voltage generating terminal during a multi-chip product test of the DRAM to cut down expenses, and to overcome load or noise due to the forcing pad by cutting (switching off) the fuse after a wafer level test during a normal operation.

    摘要翻译: 本文描述了一种用于半导体存储器件的内部电压产生装置。 内部电压发生装置被配置为通过在DRAM的多芯片产品测试期间将迫击焊盘和熔丝(或开关)安装在初始参考电压产生端子中来执行具有少量焊盘的内部电压裕度测试 并且在正常操作期间通过在晶圆级测试之后切断(断开)熔断器来克服由于强迫焊盘引起的负载或噪声。

    Method for fabricating a semiconductor device

    公开(公告)号:US06333249B2

    公开(公告)日:2001-12-25

    申请号:US09751941

    申请日:2001-01-02

    IPC分类号: H01L213205

    摘要: A method for fabricating a semiconductor device is disclosed. In a process for fabricating a CMOS transistor of a high integrated semiconductor device and a cell of a DRAM, a process for forming a dual gate electrode having a layered structure of a tungsten layer and a polysilicon layer includes the steps of forming a gate electrode shape from an undoped polysilicon layer, forming an insulating film spacer at sidewalls of the polysilicon layer, forming an LDD region, removing a portion of the undoped polysilicon layer to leave a predetermined thickness and to form an opening in which the tungsten layer will be formed, and respectively implanting different impurity ions into the undoped polysilicon layer respectively formed in the PMOS region and the NMOS region before forming the tungsten layer. Thus, it is possible to prevent etching residue from occurring and also prevent the semiconductor substrate from being damaged. In addition, it is possible to prevent the tungsten layer from being oxidized due to a high temperature process such as an ion plantation process for forming the LDD region and the source/drain region, thereby improving operational characteristics of the device and process yield.

    DATA OUTPUT DRIVER
    19.
    发明申请
    DATA OUTPUT DRIVER 审中-公开
    数据输出驱动器

    公开(公告)号:US20090206873A1

    公开(公告)日:2009-08-20

    申请号:US12329081

    申请日:2008-12-05

    申请人: Jun Gi Choi

    发明人: Jun Gi Choi

    IPC分类号: H03K17/16 H03K19/0175

    摘要: A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal.

    摘要翻译: 数据输出驱动器装置包括:噪声检测单元,被配置为输出噪声检测信号以检测由于噪声引起的电源电压的变化;以及驱动器电路单元,被配置为响应于噪声检测而以可变驱动能力驱动和输出数据 信号。

    Internal voltage generating circuit
    20.
    发明授权
    Internal voltage generating circuit 失效
    内部电压发生电路

    公开(公告)号:US06922098B2

    公开(公告)日:2005-07-26

    申请号:US10737359

    申请日:2003-12-16

    IPC分类号: G11C5/14 H03K19/0185 G05F1/10

    CPC分类号: H03K19/018585

    摘要: The present invention relates to an active driver for generating an internal voltage. In an active operation of a semiconductor device, after a voltage drop of a core voltage (VCORE) by consumed current of the core voltage (VCORE) is detected in a multi-step, a corresponding transistor for a driver is variably operated depending on a detected voltage drop level. Therefore, in an active operation, an increase in an active consumption current depending on an increase in the size of an output driver can be minimized.

    摘要翻译: 本发明涉及用于产生内部电压的有源驱动器。 在半导体器件的有源操作中,在以多步检测到核心电压(VCORE)的消耗电流的核心电压(VCORE)的电压下降之后,用于驱动器的相应晶体管可根据 检测到电压降电平。 因此,在主动操作中,可以将输出驱动器的尺寸的增加的有效消耗电流的增加最小化。