公开(公告)号：US20080026540A1

公开(公告)日：2008-01-31

申请号：US11492649

申请日：2006-07-25

申请人： Jin Ping Liu

发明人： Jin Ping Liu

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848

摘要： Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down through the strained layer and the stressor layer to as least partially expose the buried doped regions. We etch the buried doped regions to form at least a buried cavity in communication with the STI trenches. In the first and second embodiments, we fill only the STI trenches with insulation material to form isolation regions and form voids in the cavities. In the third and fourth embodiments, we fill both the STI trenches and the cavities with insulation material.

摘要翻译： 制造半导体器件的隔离区域的结构和方法。 示例方法包括以下。 我们在衬底中形成一个或多个掩埋掺杂区域。 我们在衬底上形成一个应力层。 我们在应力层上形成一个应变层。 我们通过应变层和应力层向下形成STI沟槽以至少部分地暴露掩埋的掺杂区域。 我们蚀刻掩埋的掺杂区域以形成至少与STI沟槽连通的掩埋腔。 在第一和第二实施例中，我们仅用绝缘材料填充STI沟槽以形成隔离区域并在空腔中形成空隙。 在第三和第四实施例中，我们用绝缘材料填充STI沟槽和空腔。

公开(公告)号：US20090146181A1

公开(公告)日：2009-06-11

申请号：US11952939

申请日：2007-12-07

申请人： Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

发明人： Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.

摘要翻译： 一种集成电路系统，包括：提供包括掺杂外延层的PFET器件; 以及通过使用能量源从掺杂的外延层扩散掺杂剂形成源极/漏极扩展。

公开(公告)号：US07064037B2

公开(公告)日：2006-06-20

申请号：US10755501

申请日：2004-01-12

申请人： Jin Ping Liu

发明人： Jin Ping Liu

IPC分类号： H01L21/336 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L29/78 ,  H01L29/1054

摘要： A method of forming a relaxed silicon-germanium layer for accommodation of an overlying silicon layer formed with tensile strain, has been developed. The method features growth of multiple composite layers on a semiconductor substrate, with each composite layer comprised of an underlying silicon-germanium-carbon layer and of an overlying silicon-germanium layer, followed by the growth of an overlying thicker silicon-germanium layer. A hydrogen anneal procedure performed after growth of the multiple composite layers and of the thicker silicon-germanium layer, results in a top composite layer now comprised with an overlying relaxed silicon-germanium layer, exhibiting a low dislocation density. The presence of silicon-carbon micro crystals in each silicon-germanium-carbon layer reduces the formation of, and the propagation of threading dislocations in overlying silicon-germanium layers, therefore also reducing extension of these defects into an overlying silicon layer, wherein the tensile strained silicon layer will be used to accommodate a subsequent device structure.

摘要翻译： 已经开发了形成用于容纳形成有拉伸应变的上覆硅层的松弛硅 - 锗层的方法。 该方法的特征是在半导体衬底上生长多个复合层，其中每个复合层由下面的硅 - 锗 - 碳层和上覆的硅 - 锗层组成，随后生长上覆的较厚的硅 - 锗层。 在多个复合层和更厚的硅 - 锗层的生长之后执行的氢退火程序导致顶层复合层现在包含具有低位错密度的上覆松弛硅 - 锗层。 在每个硅 - 锗 - 碳层中硅 - 碳微晶的存在减少了覆盖硅 - 锗层中穿透位错的形成和扩散，因此也减少了这些缺陷扩展到上覆硅层，其中拉伸 应变硅层将用于适应随后的器件结构。