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    Integration for buried epitaxial stressor
    4.
    发明授权
    Integration for buried epitaxial stressor 有权
    嵌入式外延应力集成

    公开(公告)号：US07863141B2

    公开(公告)日：2011-01-04

    申请号：US11492649

    申请日：2006-07-25

    申请人： Jin Ping Liu

    发明人： Jin Ping Liu

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848

    摘要： Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down through the strained layer and the stressor layer to as least partially expose the buried doped regions. We etch the buried doped regions to form at least a buried cavity in communication with the STI trenches. In the first and second embodiments, we fill only the STI trenches with insulation material to form isolation regions and form voids in the cavities. In the third and fourth embodiments, we fill both the STI trenches and the cavities with insulation material.

    摘要翻译： 制造半导体器件的隔离区域的结构和方法。 示例方法包括以下。 我们在衬底中形成一个或多个掩埋掺杂区域。 我们在衬底上形成一个应力层。 我们在应力层上形成一个应变层。 我们通过应变层和应力层向下形成STI沟槽以至少部分地暴露掩埋的掺杂区域。 我们蚀刻掩埋的掺杂区域以形成至少与STI沟槽连通的掩埋腔。 在第一和第二实施例中，我们仅用绝缘材料填充STI沟槽以形成隔离区域并在空腔中形成空隙。 在第三和第四实施例中，我们用绝缘材料填充STI沟槽和空腔。

    Integration for buried epitaxial stressor
    7.
    发明申请
    Integration for buried epitaxial stressor 有权
    嵌入式外延应力集成

    公开(公告)号：US20080026540A1

    公开(公告)日：2008-01-31

    申请号：US11492649

    申请日：2006-07-25

    申请人： Jin Ping Liu

    发明人： Jin Ping Liu

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848

    摘要： Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down through the strained layer and the stressor layer to as least partially expose the buried doped regions. We etch the buried doped regions to form at least a buried cavity in communication with the STI trenches. In the first and second embodiments, we fill only the STI trenches with insulation material to form isolation regions and form voids in the cavities. In the third and fourth embodiments, we fill both the STI trenches and the cavities with insulation material.

    摘要翻译： 制造半导体器件的隔离区域的结构和方法。 示例方法包括以下。 我们在衬底中形成一个或多个掩埋掺杂区域。 我们在衬底上形成一个应力层。 我们在应力层上形成一个应变层。 我们通过应变层和应力层向下形成STI沟槽以至少部分地暴露掩埋的掺杂区域。 我们蚀刻掩埋的掺杂区域以形成至少与STI沟槽连通的掩埋腔。 在第一和第二实施例中，我们仅用绝缘材料填充STI沟槽以形成隔离区域并在空腔中形成空隙。 在第三和第四实施例中，我们用绝缘材料填充STI沟槽和空腔。

    Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch
    9.
    发明授权
    Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
    在具有大晶格失配的衬底上形成松散半导体缓冲层的方法

    公开(公告)号：US06995078B2

    公开(公告)日：2006-02-07

    申请号：US10763305

    申请日：2004-01-23

    申请人： Jin Ping Liu ,  Dong Kyun Sohn ,  Liang Choo Hsia

    发明人： Jin Ping Liu ,  Dong Kyun Sohn ,  Liang Choo Hsia

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/0262 ,  H01L29/1054 ,  Y10S438/933

    摘要： A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses. In situ growth of an overlying silicon—germanium layer featuring uniform or non—graded germanium content, results in a relaxed silicon—germanium layer with a minimum of dislocations propagating from the underlying graded silicon—germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.

    摘要翻译： 已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。 该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长 的分级第一硅锗层进行。 该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。 具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。 硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

    Strained channel transistor structure and method
    10.
    发明授权
    Strained channel transistor structure and method 有权
    应变通道晶体管结构和方法

    公开(公告)号：US07776699B2

    公开(公告)日：2010-08-17

    申请号：US12025788

    申请日：2008-02-05

    申请人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

    发明人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

    IPC分类号： H01L29/778

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636

    摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

    摘要翻译： 一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变 底物。