公开(公告)号：US07320115B2

公开(公告)日：2008-01-15

申请号：US11180743

申请日：2005-07-12

申请人： Feng-Ming Kuo

发明人： Feng-Ming Kuo

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F11/07 ,  G01R31/28 ,  G01R31/08

CPC分类号： G06F17/5081 ,  G01R31/318342

摘要： A method is disclosed for identifying a physical failure location on an IC without using layout-versus-schematic (LVS) verification tool. In the method, the integrated circuit is tested with one or more test patterns to identify a failure port thereon. Hierarchical information of the failure port is generated through the test patterns. A physical location of the failure port in a layout of the integrated circuit is identified through a relation between the hierarchical information and a floor plan report. Layout information of a routing path associated with the physical location of the failure port is retrieved from a layout database.

摘要翻译： 公开了一种用于识别IC上的物理故障位置的方法，而不使用布局相对于示意图（LVS）验证工具。 在该方法中，利用一个或多个测试模式来测试集成电路以识别其上的故障端口。 故障端口的分层信息通过测试模式生成。 集成电路布局中的故障端口的物理位置通过分层信息和平面图报告之间的关系来识别。 从布局数据库检索与故障端口的物理位置相关联的路由路径的布局信息。

公开(公告)号：US07020536B2

公开(公告)日：2006-03-28

申请号：US10708059

申请日：2004-02-06

申请人： Long-Hui Lin ,  Feng-Ming Kuo ,  Su-Fen Cheng

发明人： Long-Hui Lin ,  Feng-Ming Kuo ,  Su-Fen Cheng

IPC分类号： G06F19/00

CPC分类号： G01N21/93 ,  Y10S707/99943

摘要： First, a wafer with a plurality of defects generated in a first semiconductor process is provided. A defect inspection is performed to detect the defects on the wafer. Then, an automatic defect classification is performed according to a predetermined defect database having a defect classification recipe generated from a second semiconductor process. After that, a verifying process is further performed by comparing the result of the automatic defect classification with that of a manual defect classification to verify the accuracy of the automatic defect classification.

摘要翻译： 首先，提供在第一半导体工艺中产生的具有多个缺陷的晶片。 执行缺陷检查以检测晶片上的缺陷。 然后，根据具有从第二半导体处理产生的缺陷分类配方的预定缺陷数据库执行自动缺陷分类。 之后，通过将自动缺陷分类的结果与手动缺陷分类的结果进行比较来进一步执行验证处理，以验证自动缺陷分类的准确性。

公开(公告)号：US06808985B1

公开(公告)日：2004-10-26

申请号：US10082021

申请日：2002-02-21

申请人： Kuei-Ying Lee ,  Shao-Yu Chou ,  Jiun-Nan Chen ,  Yue-Der Chih ,  Sam Sheng-Deh Chu ,  Feng-Ming Kuo

发明人： Kuei-Ying Lee ,  Shao-Yu Chou ,  Jiun-Nan Chen ,  Yue-Der Chih ,  Sam Sheng-Deh Chu ,  Feng-Ming Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11293 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11546

摘要： A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming simulations on the prototype, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line by skipping certain Flash/EEPROM steps and then implanting the ROM code into the final ROM product. The method improves turn-around-time in the manufacturing line, and reduces cost to the customer. A method of doing business is also disclosed directed to providing ROM products to a customer without much redesign time and effort on the part of the customer.

摘要翻译： 公开了通过使用嵌入式闪存/ EEPROM原型来制造ROM产品的方法。 这是通过首先形成闪存/ EEPROM原型，对原型进行编程仿真，开发ROM代码和掩码，然后通过跳过某些闪存/ EEPROM步骤在同一生产线上形成ROM产品，然后植入ROM代码 进入最终的ROM产品。 该方法提高了生产线的周转时间，降低了客户的成本。 还公开了一种开展业务的方法，其目的是向客户提供ROM产品，而不需要客户的重新设计时间和精力。