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11.发明申请DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCTIVE-READ MEMORY CACHE 失效破坏性阅读随机访问记忆体系统与破坏性阅读记忆体缓存公开(公告)号：US20050226083A1
公开(公告)日：2005-10-13
申请号：US11160220
申请日：2005-06-14
申请人： Brian Ji , Chorng-Lii Hwang , Toshiaki Kirihata , Seiji Munetoh
发明人： Brian Ji , Chorng-Lii Hwang , Toshiaki Kirihata , Seiji Munetoh
IPC分类号： G06F12/00 , G06F12/08 , G11C7/10 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/4093
CPC分类号： G11C8/12 , G06F12/0804 , G06F12/0893 , G06F12/0897 , G06F2212/3042 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C11/4093 , G11C2207/2245
摘要： A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.
摘要翻译： 存储器存储系统包括多个存储器存储体和与之通信的高速缓冲存储器。 多个存储器存储体和高速缓存还包括配置用于对其进行延迟回写调度的破坏性读取存储器存储元件。
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12.发明授权Destructive-read random access memory system buffered with destructive-read memory cache 失效破坏性读取随机存取存储器系统用破坏性内存缓存缓冲公开(公告)号：US06801980B2
公开(公告)日：2004-10-05
申请号：US10063466
申请日：2002-04-25
IPC分类号： G06F1200
CPC分类号： G11C8/12 , G06F12/0804 , G06F12/0893 , G06F12/0897 , G06F2212/3042 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C11/4093 , G11C2207/2245
摘要： A memory storage system is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements.
摘要翻译： 公开了一种存储器存储系统。 在示例性实施例中，存储器存储系统包括多个存储器存储体和与其通信的高速缓存器。 多个存储器存储体和高速缓存还包括破坏性读取存储器存储元件。
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13.发明授权公开(公告)号：US06674673B1
公开(公告)日：2004-01-06
申请号：US10064867
申请日：2002-08-26
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
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公开(公告)号：US06238963B1
公开(公告)日：2001-05-29
申请号：US09447631
申请日：1999-11-23
申请人： Bomy A. Chen , Chorng-Lii Hwang
发明人： Bomy A. Chen , Chorng-Lii Hwang
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/3212 , H01L27/10852 , H01L28/55
摘要： The difficulty of etching noble metals in ferroelectric capacitors is eliminated by a damascene process that employs chemical-mechanical polishing to remove the unwanted material, resulting in a lower electrode formed in an aperture in a dielectric, having a flat central portion and a wall extending from the central portion to the top surface of the surrounding dielectric; and an upper electrode formed in a two-level aperture, so that the upper electrode structure has a flat central portion, a first vertical wall extending from the central portion to a rim surrounding the central portion and extending over the wall of the lower electrode, and a second vertical wall extending from the rim to the top surface of a surrounding dielectric.
摘要翻译： 通过使用化学机械抛光去除不想要的材料的镶嵌工艺来消除在铁电电容器中蚀刻贵金属的难度，导致形成在电介质的孔中的下电极，具有平坦的中心部分和从 围绕电介质顶表面的中心部分; 以及形成在两级孔中的上电极，使得上电极结构具有平坦的中心部分，从中心部分延伸到围绕中心部分并在下电极的壁上延伸的边缘的第一垂直壁， 以及从边缘延伸到周围电介质的顶表面的第二垂直壁。
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