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公开(公告)号：US06674673B1
公开(公告)日：2004-01-06
申请号：US10064867
申请日：2002-08-26
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
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2.发明授权Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture 有权用于微电池嵌入式DRAM（e-DRAM）架构的列冗余系统和方法公开(公告)号：US06674676B1
公开(公告)日：2004-01-06
申请号：US10444226
申请日：2003-05-23
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
摘要翻译： 一种列冗余系统，包括用于执行各个微单元内的列元素的冗余交换操作的列冗余设备。 列冗余装置还包括熔丝信息存储装置，第一存储体地址解码机构对与读取操作相关的第一微小区对应的读存储体地址进行解码，第二存储体地址解码机构对与 访问用于写操作的第二微小区。 如果存在包含在第一微单元内的至少一个有缺陷的列元素，则列冗余设备生成与第一微单元中的至少一个缺陷列元素对应的内部列地址。 类似地，如果在第二微小区内包含至少一个有缺陷的列元素，则列冗余设备产生对应于第二微小区中的至少一个缺陷列元素的内部列地址。
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3.发明申请DESIGN STRUCTURE FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES 有权改善电动可编程熔断器感应尺寸的设计结构公开(公告)号：US20080030260A1
公开(公告)日：2008-02-07
申请号：US11872273
申请日：2007-10-15
申请人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
发明人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
IPC分类号： H01H37/76
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括 所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。
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公开(公告)号：US20080025071A1
公开(公告)日：2008-01-31
申请号：US11868046
申请日：2007-10-05
申请人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
发明人： Darren Anand , Gregory Fredeman , Toshiaki Kirihata , Alan Leslie , John Safran
IPC分类号： G11C11/00
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.
摘要翻译： 用于确定可编程电阻性存储元件的状态的方法包括使第一电平电流通过包括可编程电阻存储器元件的测试电路的熔丝支脚和参考电阻支路; 检测作为第一电流电平的结果，在测试电路的参考节点和熔丝节点之间产生的差分信号; 使第二电流通过保险丝支脚和测试电路的参考支路，第二电平电流高于第一电流电平，以便能够以比与第一电平相比更低的值检测测试电路的跳闸电阻 尊重目前的一级; 以及作为所述第二电流电平的结果，检测在所述参考节点和所述测试电路的所述熔丝节点之间产生的差分信号。
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公开(公告)号：US20050193253A1
公开(公告)日：2005-09-01
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
发明人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。
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6.发明申请Method and structure for enabling a redundancy allocation during a multi-bank operation 失效在多行操作期间实现冗余分配的方法和结构公开(公告)号：US20050180230A1
公开(公告)日：2005-08-18
申请号：US10777596
申请日：2004-02-12
CPC分类号： G11C29/4401 , G11C29/40 , G11C29/44 , G11C29/808 , G11C2029/0401 , G11C2029/2602
摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.
摘要翻译： 描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。 该方法包括启用通过/故障位检测来激活给定的存储体的步骤。 通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。 通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。 该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。 当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。
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公开(公告)号：US20050122801A1
公开(公告)日：2005-06-09
申请号：US11031138
申请日：2005-01-07
申请人： Louis Hsu , Gregory Fredeman , Rajiv Joshi , Toshiaki Kirihata
发明人： Louis Hsu , Gregory Fredeman , Rajiv Joshi , Toshiaki Kirihata
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size. Furthermore, a method is provided for replacing faulty wordlines of a memory array including the steps of: selecting a repair field size; storing at least one faulty address into a first memory; and copying the stored at least one faulty address from the first memory into a variable number of storage cells of a second memory, wherein each storage cell of said second memory corresponds to a respective bank of said plurality of banks; and wherein the variable number of storage cells is in accordance with the selected repair field size.
摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。 此外，提供了一种用于替换存储器阵列的错误字线的方法，包括以下步骤：选择修复字段大小; 将至少一个故障地址存储到第一存储器中; 以及将存储的至少一个故障地址从第一存储器复制到第二存储器的可变数量的存储单元中，其中所述第二存储器的每个存储单元对应于所述多个存储体的相应存储体; 并且其中所述可变数量的存储单元符合所选择的修复字段大小。
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8.发明申请公开(公告)号：US20050013185A1
公开(公告)日：2005-01-20
申请号：US10604375
申请日：2003-07-15
申请人： Hoki Kim , Toshiaki Kirihata , David Hanson , Gregory Fredeman , John Golz
发明人： Hoki Kim , Toshiaki Kirihata , David Hanson , Gregory Fredeman , John Golz
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C2207/104
摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.
摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。
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公开(公告)号：US20060039226A1
公开(公告)日：2006-02-23
申请号：US11205565
申请日：2005-08-17
申请人： David Hanson , Gregory Fredeman , John Golz , Hoki Kim , Paul Parries
发明人： David Hanson , Gregory Fredeman , John Golz , Hoki Kim , Paul Parries
IPC分类号： G11C5/14
摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。
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10.发明申请PROGRAMMING AND DETERMINING STATE OF ELECTRICAL FUSE USING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES 失效使用具有多个导通状态的场效应晶体管编程和确定电子熔丝状态公开(公告)号：US20060273841A1
公开(公告)日：2006-12-07
申请号：US11160056
申请日：2005-06-07
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or “low” conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.
摘要翻译： 提供了一种电路，其可操作以将电可更改元件（例如，熔丝或反熔丝）编程到编程状态，并确定电可更改元件是否处于编程状态。 这种电路包括多导通状态场效应晶体管（“多状态FET”），其具有耦合到可电可变元件的源极或漏极中的至少一个，以将电流施加到电可更改元件。 多状态FET具有第一阈值电压和第二阈值电压，两者均同时有效，第二阈值电压高于第一阈值电压。 栅极可操作以控制多状态FET的操作，包括a）基本上非导通状态; b）当栅极 - 源极电压超过第一阈值电压时，第一或“低”导通状态，其中多态FET被偏置以传导相对低的幅度电流以确定保险丝的状态; 以及c）当所述栅极 - 源极电压超过所述第二阈值电压时，所述第二导电状态是所述多态FET被偏置以导通相对高的编程电流。
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