公开(公告)号：US20080311684A1

公开(公告)日：2008-12-18

申请号：US11763287

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11524

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

公开(公告)号：US08897070B2

公开(公告)日：2014-11-25

申请号：US13287343

申请日：2011-11-02

申请人： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

发明人： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/16

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11582 ,  H01L29/7926

摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

摘要翻译： 用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。 在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。 在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。 虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。 虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

公开(公告)号：US20140047904A1

公开(公告)日：2014-02-20

申请号：US13961394

申请日：2013-08-07

申请人： Alex Mak

发明人： Alex Mak

IPC分类号： G01N11/14

CPC分类号： G01N11/14

摘要： Viscosity or rheology measuring instrument utilizing Hall Effect or like magnetic coupling with parts mounted on driving and driven rotational assemblies.

摘要翻译： 使用霍尔效应或类似磁耦合的粘度或流变测量仪器，安装在驱动和驱动旋转组件上。

公开(公告)号：US09513202B2

公开(公告)日：2016-12-06

申请号：US13961394

申请日：2013-08-07

申请人： Alex Mak

发明人： Alex Mak

IPC分类号： G01N11/14

CPC分类号： G01N11/14

摘要： Viscosity or rheology measuring instrument utilizing Hall Effect or like magnetic coupling with parts mounted on driving and driven rotational assemblies.

摘要翻译： 使用霍尔效应或类似磁耦合的粘度或流变测量仪器，安装在驱动和驱动旋转组件上。

公开(公告)号：US20130107628A1

公开(公告)日：2013-05-02

申请号：US13287343

申请日：2011-11-02

申请人： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

发明人： Yingda Dong ,  Alex Mak ,  Seungpil Lee ,  Johann Alsmeier

IPC分类号： G11C16/16

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  H01L27/11582 ,  H01L29/7926

摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.