公开(公告)号：US08811075B2

公开(公告)日：2014-08-19

申请号：US13570779

申请日：2012-08-09

申请人： Hao Thai Nguyen ,  Juan Carlos Lee ,  Seungpil Lee ,  Jongmin Park ,  Man Lung Mui

发明人： Hao Thai Nguyen ,  Juan Carlos Lee ,  Seungpil Lee ,  Jongmin Park ,  Man Lung Mui

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.

摘要翻译： 在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。 在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。 考虑脉冲和验证阶段之间的间隔。 对于脉冲之后的间隔，但是在建立验证条件之前，可以将源极，位线以及可能的阱电平相等化，然后在期望的DC电平进行调节。 在验证阶段之后，但是在将存储器应用于下一个脉冲之前，源和位线电平可以均衡为直流电平。

公开(公告)号：US08169831B2

公开(公告)日：2012-05-01

申请号：US13100164

申请日：2011-05-03

申请人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

发明人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C7/02 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

摘要翻译： 提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。 预充电电路耦合到用于将节点充电到初始电压的节点。 中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。 电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。 这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

公开(公告)号：US20110205804A1

公开(公告)日：2011-08-25

申请号：US13100164

申请日：2011-05-03

申请人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

发明人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

IPC分类号： G11C16/28

CPC分类号： G11C16/26 ,  G11C7/02 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

摘要： Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

摘要翻译： 提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。 预充电电路耦合到用于将节点充电到初始电压的节点。 中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。 电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。 这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

公开(公告)号：US07795952B2

公开(公告)日：2010-09-14

申请号：US12337050

申请日：2008-12-17

申请人： Man Lung Lui ,  Seungpil Lee ,  Hao Thai Nguyen

发明人： Man Lung Lui ,  Seungpil Lee ,  Hao Thai Nguyen

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C16/30

摘要： A method is presented of setting a frequency of a clock for a charge pump system including the clock and a charge pump. This includes setting an initial value for the frequency of the clock and, while operating the charge pump system using the clock running at the initial frequency value, determining the ramp rate of an output voltage for the charge pump during a recovery phase. The frequency of the clock is then adjusted so that the ramp rate of the output voltage for the charge pump during the recovery phase falls in a range not exceeding a predetermined maximum rate. A charge pump system is also described that includes a register having a settable value, where the charge pump clock frequency is responsive to the register value, and count and comparison circuitry is connectable to receive the pump's output voltage and the clock signal and determine from them the number of clock cycles the charge pump uses to recover from a reset value to a predetermined value.

摘要翻译： 提出了一种设置包括时钟和电荷泵的电荷泵系统的时钟频率的方法。 这包括设置时钟频率的初始值，并且在使用以初始频率值运行的时钟运行电荷泵系统的同时，在恢复阶段确定电荷泵的输出电压的斜坡率。 然后调整时钟的频率，使得在恢复阶段期间电荷泵的输出电压的斜坡速率落在不超过预定最大速率的范围内。 还描述了一种电荷泵系统，其包括具有可设置值的寄存器，其中电荷泵时钟频率响应寄存器值，并且计数和比较电路可连接以接收泵的输出电压和时钟信号并从它们确定 电荷泵用于从复位值恢复到预定值的时钟周期数。

公开(公告)号：US20090323420A1

公开(公告)日：2009-12-31

申请号：US12163115

申请日：2008-06-27

申请人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

发明人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

IPC分类号： G11C16/06 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C5/147 ,  G11C7/06 ,  G11C7/067 ,  G11C8/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C27/005 ,  G11C2207/005

摘要： In a sensing method, accuracy of sensing operations, such as read or verify, in a memory device is improved by avoiding fluctuations in a sense amp supply voltage which can occur when different sense amps are strobed at different times. First and second sets of sense amps perform a sensing operation on respective storage elements, such as in an all bit line configuration. The first set of sense amps is strobed at a first time point. In response, a sensed analog level is converted to digital data. The A/D conversion relies on the sense amp supply voltage being accurate. To avoid a fluctuation in the sense amp supply voltage, a bypass path allows the storage elements associated with the first set of sense amps to continue to draw power from the sense amp supply voltage. The second set of sense amps is strobed at a later, second time point.

摘要翻译： 在感测方法中，通过避免当在不同时间选通不同的感测放大器时可能发生的感测放大器电源电压的波动，改进了存储器件中的读取或验证等感测操作的精度。 第一和第二组感测放大器对各个存储元件执行感测操作，例如以全位线配置。 第一组感测放大器在第一时间点选。 作为响应，将感测的模拟电平转换为数字数据。 A / D转换依赖于正确的读出放大器电源电压。 为了避免感测放大器电源电压的波动，旁路通路允许与第一组感测放大器相关联的存储元件继续从感测放大器电源电压获取功率。 第二组感测放大器在稍后的第二时间点被选通。

公开(公告)号：US07545678B2

公开(公告)日：2009-06-09

申请号：US11772009

申请日：2007-06-29

申请人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

发明人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/565

摘要： A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

摘要翻译： 在读取NAND串中选定的非易失性存储元件的编程条件之前，其中位线对位线噪声被放电的NAND串。 施加源电压，其提高导电NAND串中的电压。 电压升高导致噪声与相邻NAND串的电容耦合。 电流下拉器件用于在执行感测之前对每个NAND串进行放电。 在每个NAND串被连接到放电路径达预定时间量之后，NAND串的位线被耦合到电压感测组件，用于基于位线的电位感测所选择的非易失性存储元件的编程状态 。 所选择的非易失性存储元件可具有负阈值电压。 此外，与所选择的非易失性存储元件相关联的字线可以被设置为接地。

公开(公告)号：US20090003068A1

公开(公告)日：2009-01-01

申请号：US11772002

申请日：2007-06-29

申请人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

发明人： Seungpil Lee ,  Hao Thai Nguyen ,  Man Lung Mui

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5645 ,  G11C2211/565

摘要： Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

摘要翻译： 在感测NAND串中所选择的非易失性存储元件的编程条件之前，位线对位线噪声在NAND串中放电。 施加源电压，其提高导电NAND串中的电压。 电压升高导致噪声与相邻NAND串的电容耦合。 电流下拉器件用于在执行感测之前对每个NAND串进行放电。 在每个NAND串被连接到放电路径达预定时间量之后，NAND串的位线被耦合到电压感测组件，用于基于位线的电位感测所选择的非易失性存储元件的编程状态 。 所选择的非易失性存储元件可具有负阈值电压。 此外，与所选择的非易失性存储元件相关联的字线可以被设置为接地。

公开(公告)号：US08737132B2

公开(公告)日：2014-05-27

申请号：US13570826

申请日：2012-08-09

申请人： Hao Thai Nguyen ,  Juan Carlos Lee ,  Seungpil Lee ,  Jongmin Park ,  Man Lung Mui

发明人： Hao Thai Nguyen ,  Juan Carlos Lee ,  Seungpil Lee ,  Jongmin Park ,  Man Lung Mui

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.

摘要翻译： 在非易失性存储器件中，写入通常由交替的脉冲和验证操作组成。 在脉冲结束时，器件必须被正确偏置才能进行准确的校验，之后器件被重新偏置用于下一个脉冲。 在一些情况下，非易失性存储器通过交替的脉冲组编程，但对于至少一些没有任何中间验证操作的脉冲。 在一个脉冲之后，但是在将存储器偏置在下一个脉冲之前，不会中断，源和位线电平可以保持浮动。

公开(公告)号：US20130258772A1

公开(公告)日：2013-10-03

申请号：US13431670

申请日：2012-03-27

申请人： Seungpil Lee ,  Jongmin Park

发明人： Seungpil Lee ,  Jongmin Park

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C7/18 ,  G11C11/5621 ,  G11C16/0425 ,  G11C16/0433 ,  G11C2211/5641

摘要： A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions.

摘要翻译： 沿着列方向将非易失性存储器阵列分割成第一和第二部分。 第一部分具有SLC存储单元，第二部分具有MLC存储单元。 第一部分用作第二部分的快速缓存。 通过耦合到与第一部分相邻的一组读/写电路，第一部分的读/写操作进一步增强，同时每个位线的列在第一和第二部分之间的连接处可切换地切断。 以这种方式，截止位线的RC常数处于最小值，这通过读/写电路转换为更快的位线预充电。 当第二部分工作时，其通过不切断第一和第二部分之间的连接处的每个位线来实现对该组读/写电路的访问。

公开(公告)号：US20130223155A1

公开(公告)日：2013-08-29

申请号：US13403934

申请日：2012-02-23

申请人： Ken Oowada ,  Yingda Dong ,  Gerrit Jan Hemink ,  Man Lung Mui ,  Hao Nguyen ,  Seungpil Lee ,  Jong Park ,  Fanglin Zhang

发明人： Ken Oowada ,  Yingda Dong ,  Gerrit Jan Hemink ,  Man Lung Mui ,  Hao Nguyen ,  Seungpil Lee ,  Jong Park ,  Fanglin Zhang

IPC分类号： G11C16/10

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3481 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028

摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

摘要翻译： 执行编程和读取过程的非易失性存储系统。 编程过程包括粗/精编程和验证操作。 通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得 两个有效的测试阈值电压水平在温度变化上保持恒定。