公开(公告)号：US20080311684A1

公开(公告)日：2008-12-18

申请号：US11763287

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11524

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

公开(公告)号：US20080310242A1

公开(公告)日：2008-12-18

申请号：US11763292

申请日：2007-06-14

申请人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

发明人： Loc Tu ,  Jian Chen ,  Alex Mak ,  Tien-chien Kuo ,  Long Pham

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/88 ,  G11C5/04

摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

摘要翻译： 存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。 在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。 为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。 封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

公开(公告)号：US08116139B2

公开(公告)日：2012-02-14

申请号：US12697003

申请日：2010-01-29

申请人： Tien-chien Kuo ,  Man L. Mui

发明人： Tien-chien Kuo ,  Man L. Mui

IPC分类号： G11C11/34

CPC分类号： G11C5/14 ,  G11C7/10 ,  G11C16/06

摘要： A power supply and monitoring apparatus such as in a nonvolatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing operation, such as a read or verify operation, a discharge period is set in which a sense node of each sense module discharges into the associated bit line and string of non-volatile storage elements, when the string of non-volatile storage elements, is conductive. This discharge sinks current from the power supply, causing a perturbation. By sampling the power supply, a steady state condition can be detected from a rate of change. The steady state condition signals that the discharge period can be concluded and data can be latched from the sense node. The discharge period automatically adapts to different memory devices and environmental conditions.

摘要翻译： 一种电源和监视装置，例如在非易失性存储器系统中。 电源电路为大量的感测模块提供电力，每个感测模块与位线和一串非易失性存储元件相关联。 在诸如读取或验证操作的感测操作期间，设置放电周期，其中每个感测模块的感测节点放电到相关联的位线和非易失性存储元件串中，当非易失性存储器串 元件，是导电的。 该放电从电源吸收电流，引起扰动。 通过对电源进行采样，可以从变化率检测稳定状态。 稳态条件指示放电周期可以结束，数据可以从感测节点锁存。 放电周期自动适应不同的存储器件和环境条件。

公开(公告)号：US20120140559A1

公开(公告)日：2012-06-07

申请号：US13397428

申请日：2012-02-15

申请人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C2211/5641

摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

摘要翻译： 本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。 在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。 作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。 在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。 之后，只有奇数字线被编程。 数据可以被传送到在擦除之前存储多个存储单元的位的块。 在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。 之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

公开(公告)号：US20110044102A1

公开(公告)日：2011-02-24

申请号：US12544113

申请日：2009-08-19

申请人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C2211/5641

摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

摘要翻译： 本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。 在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。 作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。 在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。 之后，只有奇数字线被编程。 数据可以被传送到在擦除之前存储多个存储单元的位的块。 在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。 之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

公开(公告)号：US20120321032A1

公开(公告)日：2012-12-20

申请号：US13164618

申请日：2011-06-20

申请人： Bo Liu ,  Jongmin Park ,  Chen Chen ,  Tien-chien Kuo

发明人： Bo Liu ,  Jongmin Park ,  Chen Chen ,  Tien-chien Kuo

IPC分类号： H03K23/40

CPC分类号： G11C29/40 ,  G11C29/44

摘要： A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.

摘要翻译： 用于以N位串计数具有第一二进制值的位数M的电路包括菊花链中的N个锁存电路，其中每个锁存电路具有控制每个锁存电路处于非通过或通过状态的标签位 州。 最初，标签位根据N位串的位进行设置，其中第一个二进制值对应于无通状态。 具有脉冲串的时钟信号通过菊花链行进，以询问任何无通路锁存电路。 它可以通过任何通过锁存电路进行比赛。 然而，对于无通路锁存电路，被阻塞的前导脉冲也在标签位从不通过到通过状态的脉冲周期之后复位，以允许随后的脉冲通过。 在所有无通路锁存电路复位之后，M由脉冲序列的丢失脉冲数给出。

公开(公告)号：US08144511B2

公开(公告)日：2012-03-27

申请号：US12544113

申请日：2009-08-19

申请人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C2211/5641

摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

公开(公告)号：US20140063961A1

公开(公告)日：2014-03-06

申请号：US13605583

申请日：2012-09-06

申请人： Manabu Sakai ,  Toru Miwa ,  Tien-chien Kuo

发明人： Manabu Sakai ,  Toru Miwa ,  Tien-chien Kuo

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.

摘要翻译： 提供方法和非易失性存储系统用于在非易失性存储器的编程期间恢复数据。 最初存储在一组锁存器中的程序数据可以通过两组锁存器的组合来保存。 这两组锁存器也可用于在该程序数据的编程期间存储验证状态。 可以通过对两组锁存器中的数据执行逻辑运算来恢复原始程序数据。 例如，上页数据可以最初存储在一组锁存器中。 当上位数据被编程时，该组锁存器和另一组锁存器用于存储相对于上位数据的验证状态。 如果在保留上位页数据时发生程序错误，则可以通过对两组锁存器执行逻辑运算来恢复程序错误。

公开(公告)号：US08315093B2

公开(公告)日：2012-11-20

申请号：US13397428

申请日：2012-02-15

申请人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Tien-chien Kuo ,  Gerrit Jan Hemink

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3418 ,  G11C2211/5641

摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

摘要翻译： 本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。 在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。 作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。 在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。 之后，只有奇数字线被编程。 数据可以被传送到在擦除之前存储多个存储单元的位的块。 在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。 之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

公开(公告)号：US09135989B2

公开(公告)日：2015-09-15

申请号：US13605583

申请日：2012-09-06

申请人： Manabu Sakai ,  Toru Miwa ,  Tien-chien Kuo

发明人： Manabu Sakai ,  Toru Miwa ,  Tien-chien Kuo

IPC分类号： G11C11/34 ,  G11C11/56

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.

摘要翻译： 提供方法和非易失性存储系统用于在非易失性存储器的编程期间恢复数据。 最初存储在一组锁存器中的程序数据可以通过两组锁存器的组合来保存。 这两组锁存器也可用于在该程序数据的编程期间存储验证状态。 可以通过对两组锁存器中的数据执行逻辑运算来恢复原始程序数据。 例如，上页数据可以最初存储在一组锁存器中。 当上位数据被编程时，该组锁存器和另一组锁存器用于存储相对于上位数据的验证状态。 如果在保留上位页数据时发生程序错误，则可以通过对两组锁存器执行逻辑运算来恢复程序错误。