公开(公告)号：US20170077940A1

公开(公告)日：2017-03-16

申请号：US15261536

申请日：2016-09-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro YOSHIOKA ,  Tetsuro ITAKURA ,  Masanori FURUTA

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/164 ,  H03M1/185

Abstract: An A/D converter circuit has an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal, a first sampling circuit to sample the first amplification signal, a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal, a second sampling circuit to sample the second amplification signal, a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal, a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal, and a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.

Abstract translation: A / D转换器电路具有放大电路，用于放大输入信号并输出​​第一放大信号和第二放大信号，第二放大信号的放大误差小于第一放大信号中的放大误差，第一采样电路采样 第一放大信号，第一A / D转换器，用于对由第一采样电路采样的第一放大信号执行A / D转换，并输出第一数字信号;第二采样电路，对第二放大信号进行采样; D / A 转换器，对第一数字信号执行D / A转换，并输出第一模拟信号;减法器，从第二采样电路采样的第二放大信号中减去第一模拟信号，并输出第二模拟信号;第二A / D转换器对第二模拟信号执行A / D转换并输出第二数字信号。

公开(公告)号：US20170059631A1

公开(公告)日：2017-03-02

申请号：US15244353

申请日：2016-08-23

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro YOSHIOKA ,  Tetsuro ITAKURA ,  Masanori FURUTA

IPC: G01R19/252 ,  H03M1/46

CPC classification number: G01R19/252 ,  H03M1/0695 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/46

Abstract: An A/D converter has an analog input terminal, an analog output terminal, a digital output terminal, a first resistance comprising one end connected to the analog input terminal or a reference voltage line and another end connected to a first node, a second resistance comprising one end connected to the first node and another end connected to the analog output terminal, an operational amplifier comprising a first input terminal connected to the first node, a second input terminal connected to the reference voltage line or the analog input terminal, and an output terminal connected to the analog output terminal, a quantizer comprising an input terminal connected to the analog input terminal and an output terminal connected to the digital output terminal, and a DA converter comprising an input terminal connected to the digital output terminal and an output terminal connected to the first node.

Abstract translation: A / D转换器具有模拟输入端子，模拟输出端子，数字输出端子，包括连接到模拟输入端子的一端或参考电压线的第一电阻，以及连接到第一节点的另一端，第二电阻 包括连接到所述第一节点的一端和连接到所述模拟输出端子的另一端，运算放大器，包括连接到所述第一节点的第一输入端子，连接到所述参考电压线或所述模拟输入端子的第二输入端子，以及 输出端子连接到模拟输出端子，量化器包括连接到模拟输入端子的输入端子和连接到数字输出端子的输出端子，以及DA转换器，包括连接到数字输出端子的输入端子和输出端子 连接到第一个节点。

公开(公告)号：US20160352349A1

公开(公告)日：2016-12-01

申请号：US15163916

申请日：2016-05-25

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro YOSHIOKA ,  Masanori FURUTA ,  Junya MATSUNO ,  Tetsuro ITAKURA

IPC: H03M1/12 ,  H03F3/45 ,  H03F1/34 ,  H03K3/03

CPC classification number: H03M1/124 ,  H03F1/34 ,  H03F3/45 ,  H03F2200/294 ,  H03K3/0315 ,  H03M1/361 ,  H03M1/46 ,  H03M3/32

Abstract: An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

Abstract translation: 放大器电路具有采样电路，其包括对输入电压和多个开关进行采样的采样电容器，用于量化采样电路的输出电压的量化器，DA转换器，用于根据量化信号输出模拟信号 量化器和反馈电容器将模拟信号反馈到采样电路的输出电压。

公开(公告)号：US20220190812A1

公开(公告)日：2022-06-16

申请号：US17468431

申请日：2021-09-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yosuke TOYAMA ,  Tuan Thanh TA ,  Satoshi KONDO ,  Akihide SAI ,  Toshiki SUGIMOTO ,  Kentaro YOSHIOKA

IPC: H03K3/03 ,  G04F10/00

Abstract: An oscillation circuit has a first oscillator having output nodes of n stages, where n is an integer of 3 or more, a second oscillator having output nodes of n stages, and a third oscillator having output nodes of n stages. An output node at an a-th stage of the first oscillator and an output node at an a-th stage of the second oscillator are connected with each other, where a is an integer of 1 or more and n or less and an output node at a b-th stage of the second oscillator and an output node at a b-th stage of the third oscillator are connected with each other, where b is an integer of 1 or more and n or less different from a.

公开(公告)号：US20220182067A1

公开(公告)日：2022-06-09

申请号：US17468493

申请日：2021-09-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Toshiki SUGIMOTO ,  Kentaro YOSHIOKA ,  Akihide SAI ,  Yosuke TOYAMA

IPC: H03M1/12

Abstract: An analog-to-digital converter has a first digital signal generator that generates a first digital signal based on whether or not a sampling signal of an input signal is equal to or lower than a signal corresponding to a second reference signal higher than a first reference signal, a first slope generator to generate a first slope signal that changes with time from the sampled and held signal equal to or lower than the first reference signal, a second slope generator to generate a second slope signal that changes with time from the sampled and held signal to a signal level equal to or lower than the second reference signal, and a second digital signal generator that generates a second digital signal based on a time at which the first slope signal matches the first reference signal or a time at which the second slope signal matches the second reference signal.

公开(公告)号：US20220163658A1

公开(公告)日：2022-05-26

申请号：US17469445

申请日：2021-09-08

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro YOSHIOKA ,  Kazuhiro TSUJIMURA ,  Hiroki MORI

IPC: G01S13/88 ,  G01S13/68 ,  G01S13/56 ,  G01S13/89 ,  G01S13/28 ,  G01S13/86 ,  G01S7/41

Abstract: According to one embodiment, a system includes a radar device, a storage device and a controller. The radar device is configured to transmit a first radio wave to an object in a direction of a first angle of the object. The storage device is configured to store first information capable of specifying that a radio wave is transmitted to the first angle of the object by the radar device. The controller is configured to control a direction of a second radio wave to be transmitted by the radar device after the transmission of the first radio wave to a second angle of the object different from the first angle.

公开(公告)号：US20210116676A1

公开(公告)日：2021-04-22

申请号：US17019874

申请日：2020-09-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hidenori OKUNI ,  Kentaro YOSHIOKA ,  Tetsuro ITAKURA

IPC: G02B7/182 ,  G01S17/42 ,  G01S17/89

Abstract: A system has receiver circuitry configured to receive mirror information including at least one of a position, size, height, or an angle of the mirror and surrounding information acquired by measurement of at least part of surrounding of the mirror, and processing circuitry configured to specify a first range observable via a reflection in the mirror, estimate, based on the surrounding information, a second range observable via a reflection in the mirror whose at least one of the position, size, height, or angle is changed, and generate adjustment information used to adjust at least one of the position, height, or angle of the mirror in accordance with the first range information and the second range information.

公开(公告)号：US20190288703A1

公开(公告)日：2019-09-19

申请号：US16126477

申请日：2018-09-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro YOSHIOKA

IPC: H03M1/82

Abstract: A digital-to-time converter has an oscillator; and count circuitry that starts counting a number of oscillations of the oscillator when an activation signal is input, and outputs a first delay activation signal obtained by delaying the activation signal during a period from a timing when the activation signal is input to a timing when a counted number of oscillations reaches a reference number set based on a digital input signal.