ANALOG-TO-DIGITAL CONVERSION SYSTEM AND ANALOG-TO-DIGITAL CONVERSION METHOD

    公开(公告)号:US20230188154A1

    公开(公告)日:2023-06-15

    申请号:US17953449

    申请日:2022-09-27

    IPC分类号: H03M1/36

    CPC分类号: H03M1/361

    摘要: An analog-to-digital conversion system includes: a first conversion device configured to communicate with a first analog-to-digital converter configured to convert a first analog signal into a first digital signal; a second conversion device configured to communicate with a second analog-to-digital converter configured to convert a second analog signal into a second digital signal; a first reference low power supply; and a second reference low power supply. The first conversion device is configured to correct the first digital signal, based on a variation amount of a second reference low voltage or a second reference low current. The second conversion device is configured to correct the second digital signal, based on a variation amount of a first reference low voltage or a first reference low current.

    FILTER CIRCUIT FOR FILTERING AN INPUT SIGNAL OF AN ANALOGUE-TO-DIGITAL CONVERTER

    公开(公告)号:US20180351566A1

    公开(公告)日:2018-12-06

    申请号:US15743123

    申请日:2016-07-05

    发明人: Christian Grewing

    IPC分类号: H03M1/08 H03M1/06 H03M1/36

    摘要: The invention relates to a filter circuit (200) comprising at least a first filter line (210). The first filter line (210) has a first input circuit (10), a first integration circuit (20) and a first output circuit (30). The first input circuit (10) is configured in such a way that, as a function of the value of the input signal, it converts an input signal into at least two distinguishable, first first-stage output signals and relays the first-stage output signals to the first integration circuit (20, 240) during a prescribed period of time. The first integration circuit (20) is configured to integrate the first first-stage output signals of the first input circuit (10) over the prescribed period of time and to generate a first integration signal (25). The first output circuit (25) is configured to compare the first integration signal (25) to a first output reference value and to generate a first second-stage output signal (35). The invention also relates to an appertaining filtering method.

    ADC BASED RECEIVER
    8.
    发明申请
    ADC BASED RECEIVER 审中-公开

    公开(公告)号:US20180287837A1

    公开(公告)日:2018-10-04

    申请号:US15471364

    申请日:2017-03-28

    申请人: Xilinx, Inc.

    IPC分类号: H04L27/01 H04B1/06

    摘要: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

    High speed comparator with digitally calibrated threshold

    公开(公告)号:US09825642B2

    公开(公告)日:2017-11-21

    申请号:US15237565

    申请日:2016-08-15

    摘要: A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.