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公开(公告)号:US12057850B2
公开(公告)日:2024-08-06
申请号:US18195005
申请日:2023-05-09
申请人: Frank R. Dropps
发明人: Frank R. Dropps
IPC分类号: H03M1/06 , G01K1/02 , H03M1/08 , H03M1/10 , H03M1/12 , G01K1/14 , G01K3/04 , G01K7/01 , G01K7/42 , G01K13/20 , H03M1/00 , H03M1/36
CPC分类号: H03M1/06 , G01K1/02 , H03M1/0809 , H03M1/0845 , H03M1/089 , H03M1/1009 , H03M1/1071 , H03M1/12 , H03M1/1245 , G01K1/14 , G01K3/04 , G01K7/01 , G01K7/42 , G01K13/20 , G01K2219/00 , H03M1/00 , H03M1/361
摘要: Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.
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公开(公告)号:US11831326B2
公开(公告)日:2023-11-28
申请号:US17953449
申请日:2022-09-27
发明人: Takanori Satake , Yuzoh Yamauchi , Satoshi Nishio
CPC分类号: H03M1/361 , H03M1/0609 , H03M1/10 , H03M1/1028 , H03M1/36 , H03M1/38
摘要: An analog-to-digital conversion system includes: a first conversion device configured to communicate with a first analog-to-digital converter configured to convert a first analog signal into a first digital signal; a second conversion device configured to communicate with a second analog-to-digital converter configured to convert a second analog signal into a second digital signal; a first reference low power supply; and a second reference low power supply. The first conversion device is configured to correct the first digital signal, based on a variation amount of a second reference low voltage or a second reference low current. The second conversion device is configured to correct the second digital signal, based on a variation amount of a first reference low voltage or a first reference low current.
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公开(公告)号:US11716088B2
公开(公告)日:2023-08-01
申请号:US17517121
申请日:2021-11-02
申请人: Frank R. Dropps
发明人: Frank R. Dropps
IPC分类号: H03M1/06 , H03M1/12 , G01K1/02 , H03M1/08 , H03M1/10 , G01K7/01 , G01K1/14 , H03M1/00 , G01K3/04 , G01K7/42 , H03M1/36 , G01K13/20
CPC分类号: H03M1/06 , G01K1/02 , H03M1/0809 , H03M1/089 , H03M1/0845 , H03M1/1009 , H03M1/1071 , H03M1/12 , H03M1/1245 , G01K1/14 , G01K3/04 , G01K7/01 , G01K7/42 , G01K13/20 , G01K2219/00 , H03M1/00 , H03M1/361
摘要: Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.
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公开(公告)号:US20230188154A1
公开(公告)日:2023-06-15
申请号:US17953449
申请日:2022-09-27
发明人: Takanori SATAKE , Yuzoh YAMAUCHI , Satoshi NISHIO
IPC分类号: H03M1/36
CPC分类号: H03M1/361
摘要: An analog-to-digital conversion system includes: a first conversion device configured to communicate with a first analog-to-digital converter configured to convert a first analog signal into a first digital signal; a second conversion device configured to communicate with a second analog-to-digital converter configured to convert a second analog signal into a second digital signal; a first reference low power supply; and a second reference low power supply. The first conversion device is configured to correct the first digital signal, based on a variation amount of a second reference low voltage or a second reference low current. The second conversion device is configured to correct the second digital signal, based on a variation amount of a first reference low voltage or a first reference low current.
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公开(公告)号:US20180351566A1
公开(公告)日:2018-12-06
申请号:US15743123
申请日:2016-07-05
发明人: Christian Grewing
CPC分类号: H03M1/0863 , H03M1/0626 , H03M1/361
摘要: The invention relates to a filter circuit (200) comprising at least a first filter line (210). The first filter line (210) has a first input circuit (10), a first integration circuit (20) and a first output circuit (30). The first input circuit (10) is configured in such a way that, as a function of the value of the input signal, it converts an input signal into at least two distinguishable, first first-stage output signals and relays the first-stage output signals to the first integration circuit (20, 240) during a prescribed period of time. The first integration circuit (20) is configured to integrate the first first-stage output signals of the first input circuit (10) over the prescribed period of time and to generate a first integration signal (25). The first output circuit (25) is configured to compare the first integration signal (25) to a first output reference value and to generate a first second-stage output signal (35). The invention also relates to an appertaining filtering method.
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6.
公开(公告)号:US20180331690A1
公开(公告)日:2018-11-15
申请号:US15976708
申请日:2018-05-10
发明人: Jae Joon KIM , Kyeong Hwan PARK
摘要: An SAR ADC combined with a flash ADC includes a clock generator, a DAC and a comparator. The SAR ADC combined with the flash ADC further includes an SAR logic unit using a successive approximation register control to determine, while a clock signal is a first state that is either high or low, a part of digital bits of the input signal based on a signal outputted from the comparator and control the DAC to generate a first analog signal based on the first determined digital bits and a flash ADC using a flash control to determine, during a second state switched from the first state, a remaining part of the digital bits of the input signal based on the first analog signal and control the DAC to generate a second analog signal based on the second determined digital bits in the second state.
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公开(公告)号:US20180309460A1
公开(公告)日:2018-10-25
申请号:US15914833
申请日:2018-03-07
申请人: Abhishek Bandyopadhyay , Daniel Peter Canniff , Mariana Tosheva Markova , Edward Chapin Guthrie
发明人: Abhishek Bandyopadhyay , Daniel Peter Canniff , Mariana Tosheva Markova , Edward Chapin Guthrie
CPC分类号: H03M3/424 , H03M1/002 , H03M1/066 , H03M1/361 , H03M1/365 , H03M3/02 , H03M3/04 , H03M3/32 , H03M3/452 , H03M3/464
摘要: A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.
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公开(公告)号:US20180287837A1
公开(公告)日:2018-10-04
申请号:US15471364
申请日:2017-03-28
申请人: Xilinx, Inc.
发明人: Hongtao Zhang , Yohan Frans , Geoffrey Zhang
CPC分类号: H04L27/01 , H03M1/182 , H03M1/361 , H04B1/06 , H04B2203/5425 , H04L25/063 , H04Q2213/03
摘要: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.
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公开(公告)号:US09825642B2
公开(公告)日:2017-11-21
申请号:US15237565
申请日:2016-08-15
申请人: NVIDIA CORPORATION
CPC分类号: H03M1/1023 , H03K3/023 , H03M1/002 , H03M1/34 , H03M1/361
摘要: A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.
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10.
公开(公告)号:US09660660B1
公开(公告)日:2017-05-23
申请号:US15273397
申请日:2016-09-22
CPC分类号: H03M1/1023 , H03M1/069 , H03M1/124 , H03M1/1245 , H03M1/164 , H03M1/361
摘要: An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.
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