公开(公告)号：US20150130649A1

公开(公告)日：2015-05-14

申请号：US14339266

申请日：2014-07-23

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tetsuro ITAKURA ,  Masanori FURUTA ,  Akihide SAI ,  Junya MATSUNO

IPC: H03M1/06 ,  H03M1/60

CPC classification number: H03M1/0626 ,  H03M1/0607 ,  H03M1/1295 ,  H03M1/60

Abstract: In one embodiment, an AD converter includes a first (second) oscillation circuit, a first (second) counter, a first (second) arithmetic circuit, a first (second) subtracting circuit, an adder circuit, and a feedback circuit. The first oscillation circuit generates a first pulse signal having a frequency corresponding to a level of a first analog signal. The first counter counts the first pulse signal. The first arithmetic circuit generates a first signal corresponding to a change amount of a count value. The first subtracting circuit outputs a digital signal corresponding to a difference between the signals generated by the first and second arithmetic circuits. The adder circuit generates a sum signal of the signals generated by the first and second arithmetic circuits. The second subtracting circuit generates a difference signal between the sum signal and a reference signal. The feedback circuit inputs the difference signal to the first oscillation circuit.

Abstract translation: 在一个实施例中，AD转换器包括第一（第二）振荡电路，第一（第二）计数器，第一（第二）运算电路，第一（第二）减法电路，加法器电路和反馈电路。 第一振荡电路产生具有对应于第一模拟信号电平的频率的第一脉冲信号。 第一个计数器对第一个脉冲信号进行计数。 第一算术电路产生对应于计数值的变化量的第一信号。 第一减法电路输出对应于由第一和第二运算电路产生的信号之间的差值的数字信号。 加法器电路产生由第一和第二运算电路产生的信号的和信号。 第二减法电路在和信号和参考信号之间产生差分信号。 反馈电路将差分信号输入到第一振荡电路。

公开(公告)号：US20140361917A1

公开(公告)日：2014-12-11

申请号：US14297343

申请日：2014-06-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Junya MATSUNO ,  Masanori FURUTA ,  Tetsuro ITAKURA

IPC: G01R19/00 ,  G01R19/10 ,  H03M1/12

CPC classification number: G01R19/0038 ,  G01R19/10 ,  H03M1/002 ,  H03M1/206 ,  H03M1/361

Abstract: The first amplifier operates according a first clock, changes voltages of a first terminal and a second terminal from a first fixed voltage to a second fixed voltage according to a voltage of an input signal and a first reference voltage, respectively, when an on period of a first clock starts, and keeps the voltages of the first and second terminals at the second fixed voltage, respectively, after the voltages of the first and second terminals reach the second fixed voltage and until the on period of the first clock ends, and the first comparator generates first and second logic signals that have logical levels different from each other, based on a difference between the voltages of the first and second terminals when the on period of a second clock whose on period at least partially overlaps with that of the first clock starts.

Abstract translation: 第一放大器根据第一时钟进行工作，分别根据输入信号和第一参考电压的电压将第一端子和第二端子的电压从第一固定电压改变到第二固定电压，当接通时间 第一时钟开始，并且在第一和第二终端的电压达到第二固定电压并且直到第一时钟的接通周期结束之后，分别将第一和第二端子的电压保持在第二固定电压，并且 第一比较器基于第一时钟与第二时钟的接通周期至少部分重叠的第二时钟的导通周期，基于第一和第二终端的电压之间的差异，产生具有彼此不同的逻辑电平的第一和第二逻辑信号 时钟开始。

公开(公告)号：US20140045444A1

公开(公告)日：2014-02-13

申请号：US13961786

申请日：2013-08-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Masanori FURUTA ,  Junya MATSUNO

IPC: H03M1/12 ,  H04B1/16

CPC classification number: H03M1/1245 ,  G11C27/02 ,  H03F3/45968 ,  H04B1/16

Abstract: According to some embodiments, there is provided a signal sampling circuit in which the first sampling capacitor is connected to the first sampling switch, the second sampling capacitor is connected to the second sampling switch, the amplifier outputs a positive-side amplified signal by amplifying a signal input to the positive-side input terminal thereof and outputs a negative-side amplified signal by amplifying a signal input to the negative-side input terminal thereof, the first chopper switch is connected to the first sampling capacitor and the positive-side input terminal, the second chopper switch is connected to the first sampling capacitor and the negative-side input terminal, the third chopper switch is connected to the second sampling capacitor and the positive-side input terminal and the fourth chopper switch is connected to the second sampling capacitor and the negative-side input terminal.

Abstract translation: 根据一些实施例，提供了一种信号采样电路，其中第一采样电容器连接到第一采样开关，第二采样电容器连接到第二采样开关，放大器通过放大正极侧放大信号来输出正侧放大信号 信号输入到其正侧输入端，并通过放大输入到其负侧输入端的信号输出负侧放大信号，第一斩波开关连接到第一采样电容器和正侧输入端子 ，第二斩波开关连接到第一采样电容器和负侧输入端子，第三斩波开关连接到第二采样电容器，正侧输入端子和第四斩波开关连接到第二采样电容器 和负侧输入端子。

公开(公告)号：US20160352349A1

公开(公告)日：2016-12-01

申请号：US15163916

申请日：2016-05-25

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kentaro YOSHIOKA ,  Masanori FURUTA ,  Junya MATSUNO ,  Tetsuro ITAKURA

IPC: H03M1/12 ,  H03F3/45 ,  H03F1/34 ,  H03K3/03

CPC classification number: H03M1/124 ,  H03F1/34 ,  H03F3/45 ,  H03F2200/294 ,  H03K3/0315 ,  H03M1/361 ,  H03M1/46 ,  H03M3/32

Abstract: An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

Abstract translation: 放大器电路具有采样电路，其包括对输入电压和多个开关进行采样的采样电容器，用于量化采样电路的输出电压的量化器，DA转换器，用于根据量化信号输出模拟信号 量化器和反馈电容器将模拟信号反馈到采样电路的输出电压。

公开(公告)号：US20160336930A1

公开(公告)日：2016-11-17

申请号：US15092977

申请日：2016-04-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Junya MATSUNO ,  Masanori FURUTA ,  Tetsuro ITAKURA

IPC: H03K5/02 ,  H03M1/12 ,  H04B1/40 ,  G11C27/02

CPC classification number: H03K5/02 ,  G11C27/026 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2203/45138 ,  H03F2203/45551 ,  H03F2203/45634

Abstract: An amplifying circuit according to an embodiment includes an input terminal, an output terminal, first and second operational amplifiers, first and second input impedance elements, first to third feedback impedance elements, and an adder. The first (second) operational amplifier includes an inversion input terminal connected to a first (third) node and an output terminal connected to a second (fourth) node. The first (second) input impedance element has one end connected to the input terminal and the other end connected to the first (third) node. The first (second) feedback impedance element has one end connected to the first (third) node and the other end connected to the second (fourth) node. The third feedback impedance element has one end connected to the first node and the other end connected to the fourth node. The adder adds output voltages of the first and second operational amplifiers.

Abstract translation: 根据实施例的放大电路包括输入端子，输出端子，第一和第二运算放大器，第一和第二输入阻抗元件，第一至第三反馈阻抗元件以及加法器。 第一（第二）运算放大器包括连接到第一（第三）节点的反相输入端子和连接到第二（第四）节点的输出端子。 第一（第二）输入阻抗元件的一端连接到输入端，另一端连接到第一（第三）节点。 第一（第二）反馈阻抗元件的一端连接到第一（第三）节点，另一端连接到第二（第四）节点。 第三反馈阻抗元件的一端连接到第一节点，另一端连接到第四节点。 该加法器加上第一和第二运算放大器的输出电压。

公开(公告)号：US20160329881A1

公开(公告)日：2016-11-10

申请号：US15061562

申请日：2016-03-04

Applicant: KABUSHIKI KAISHA TOSHIBA ,  Tokyo University of Science Foundation

Inventor： Junya MATSUNO ,  Masanori FURUTA ,  Tetsuro ITAKURA ,  Akira HYOGO ,  Tatsuji MATSUURA ,  Takuya HARA

IPC: H03K3/0233 ,  H03M1/12 ,  H04B1/04 ,  G11C27/02

CPC classification number: H03K3/0233 ,  G11C27/026 ,  H03F1/02 ,  H03F3/24 ,  H03F3/45475 ,  H03F2203/45512 ,  H03F2203/45551 ,  H03F2203/45634 ,  H04B1/0458 ,  H04B2001/045

Abstract: An amplifying circuit according to an embodiment includes a sample and hold circuit, an operational amplifier, a feedback capacitance, and a level shift circuit. The sample and hold circuit includes a sampling capacitance to sample an analog input signal in a sampling phase. The operational amplifier amplifies and outputs the analog input signal held by the sampling capacitance in the amplifying phase. The feedback capacitance is connected between the input terminal of the operational amplifier and the analog output terminal. The level shift circuit includes a level shift capacitance to sample the analog input signal in the sampling phase. A plurality of level shift capacitances is provided and connected in cascade between the output terminal of the operational amplifier and the analog output terminal.

Abstract translation: 根据实施例的放大电路包括采样和保持电路，运算放大器，反馈电容和电平移位电路。 采样和保持电路包括采样电容，以在采样阶段对模拟输入信号进行采样。 运算放大器在放大阶段放大并输出由采样电容保持的模拟输入信号。 反馈电容连接在运算放大器的输入端和模拟输出端之间。 电平移位电路包括在采样阶段对模拟输入信号进行采样的电平移位电容。 提供多个电平移位电容并级联连接在运算放大器的输出端和模拟输出端之间。

公开(公告)号：US20150213905A1

公开(公告)日：2015-07-30

申请号：US14602351

申请日：2015-01-22

Applicant: Kabushiki Kaisha Toshiba

Inventor： Junya MATSUNO ,  Masanori FURUTA ,  Tetsuro ITAKURA

IPC: G11C27/02 ,  H03M1/12

CPC classification number: G11C27/02 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/38

Abstract: A signal processing circuit according to one embodiment includes a rectifier, a holder, a controller, and a setter. The rectifier generates a rectified voltage by rectifying an input voltage in which a signal voltage is superimposed on a common-mode voltage. The holder holds a voltage. The controller controls the holder so that the holder holds a voltage according to the rectified voltage generated by the rectifier. The setter sets the voltage held by the holder to a predetermined voltage at predetermined time intervals.

Abstract translation: 根据一个实施例的信号处理电路包括整流器，保持器，控制器和设置器。 整流器通过对信号电压叠加在共模电压上的输入电压进行整流来产生整流电压。 持有人持有电压。 控制器控制保持器，使得保持器根据整流器产生的整流电压保持电压。 固定器将保持器保持的电压以预定的时间间隔设置为预定电压。

公开(公告)号：US20180069577A1

公开(公告)日：2018-03-08

申请号：US15443541

申请日：2017-02-27

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Junya MATSUNO ,  Hidenori OKUNI ,  Masanori FURUTA ,  Tetsuro ITAKURA

IPC: H04B1/10 ,  H04L7/00 ,  H04B1/04

CPC classification number: H04B1/1027 ,  H04B1/04 ,  H04L7/0016 ,  H04L27/06

Abstract: A receiver has a receiving unit to receive a radio signal, a signal detector to detect a reception signal in each of a plurality of set periods shifted in time to be overlapped in a partial period, and a demodulating unit to perform demodulation processing based on the reception signal. The signal detector has a smoothing unit to smooth the output signal of the receiving unit in each of the plurality of set periods, a comparing unit to output a signal obtained by comparing a level of the smoothed signal, with a threshold value, and an initializing unit to initialize the signal smoothed by the smoothing processing unit, every time the comparing unit compares the smoothed signal with the threshold value, and the demodulating unit performs the demodulation processing based on the smoothed signal determined to be the threshold value or more by the comparing unit.

公开(公告)号：US20150263746A1

公开(公告)日：2015-09-17

申请号：US14657728

申请日：2015-03-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kei SHIRAISHI ,  Masanori FURUTA ,  Junya MATSUNO ,  Tetsuro ITAKURA

IPC: H03M1/08 ,  H03M1/00 ,  H03M1/66

CPC classification number: H03M1/0836 ,  H03M1/001 ,  H03M1/08 ,  H03M1/0845 ,  H03M1/66 ,  H03M1/665 ,  H03M1/742

Abstract: According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.

Abstract translation: 根据实施例，电源噪声消除电路包括发生器，第一乘法器，减法器和数模转换器。 发生器产生正弦波信号。 第一乘法器基于正弦波信号将数字输入信号乘以数字信号以产生第一数字乘积信号。 减法器基于来自数字输入信号的第一数字乘积信号减去数字信号，以产生数字差分信号。 数模转换器对数字差分信号执行数模转换以获得模拟输出信号。

公开(公告)号：US20150138007A1

公开(公告)日：2015-05-21

申请号：US14548886

申请日：2014-11-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Kei SHIRAISHI ,  Junya MATSUNO ,  Masanori FURUTA

IPC: H03M1/20 ,  H03M1/36 ,  H03M1/18 ,  H03M1/12

CPC classification number: H03M1/20 ,  H03M1/0695 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/18 ,  H03M1/36 ,  H03M1/466 ,  H03M1/56 ,  H03M3/46

Abstract: According to an embodiment, an analog-to-digital (AD) converter includes a first AD conversion unit, a selector and a second AD conversion unit. The first AD conversion unit performs AD conversion of an analog signal in a first period to generate an upper-bit digital signal. The selector selects not less than one reference voltage based on the upper-bit digital signal to obtain a selected reference voltage group in a voltage range narrower than a full scale. The second AD conversion unit performs AD conversion of the analog signal by using the selected reference voltage group. The first period starts before settling of the analog signal up to an accuracy corresponding to a total resolution of the first AD conversion unit and the second AD conversion unit.

Abstract translation: 根据实施例，模数（AD）转换器包括第一AD转换单元，选择器和第二AD转换单元。 第一AD转换单元在第一周期中执行模拟信号的AD转换，以产生高位数字信号。 选择器基于高位数字信号选择不少于一个参考电压，以在比满量程更窄的电压范围内获得所选参考电压组。 第二AD转换单元通过使用所选择的参考电压组来执行模拟信号的AD转换。 第一时段在模拟信号稳定之前开始，直到对应于第一AD转换单元和第二AD转换单元的总分辨率的精度。