公开(公告)号：US12148482B2

公开(公告)日：2024-11-19

申请号：US18348570

申请日：2023-07-07

Applicant: Kioxia Corporation

Inventor： Takeshi Hioka

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

公开(公告)号：US11810629B2

公开(公告)日：2023-11-07

申请号：US17899971

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Hioka ,  Toshifumi Watanabe

IPC: G11C16/10 ,  G11C16/34 ,  G11C7/06

CPC classification number: G11C16/3459 ,  G11C7/06 ,  G11C16/102 ,  G11C16/3404

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.

公开(公告)号：US11380406B2

公开(公告)日：2022-07-05

申请号：US17017726

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Yousuke Hagiwara ,  Kensuke Yamamoto ,  Takeshi Hioka ,  Satoshi Inoue

IPC: G11C7/00 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.

公开(公告)号：US11205482B2

公开(公告)日：2021-12-21

申请号：US16806282

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Hioka ,  Koji Kato

IPC: G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C7/22 ,  G11C16/34 ,  G11C16/04 ,  G11C16/24

Abstract: A semiconductor storage device includes a plurality of memory cells connected to each other in series, a plurality of word lines respectively connected to gates of the plurality of memory cells, and a control circuit configured to perform a read operation by applying a first voltage higher than ground voltage to the plurality of word lines during a first time period at the beginning of which each word line is at ground voltage, applying a second voltage lower than the first voltage to a first word line during a second time period subsequent to the first time period, applying a third voltage higher than the second voltage to the first word line during a third time period subsequent to the second time period, and determining data of the memory cells connected to the first word line while all portions of the first word line are at the third voltage.