公开(公告)号：US11996143B2

公开(公告)日：2024-05-28

申请号：US17846889

申请日：2022-06-22

Applicant: KIOXIA CORPORATION

Inventor： Tomoki Nakagawa ,  Koji Kato ,  Toshifumi Hashimoto

IPC: G11C16/30 ,  G11C5/14 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C5/14 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US11894070B2

公开(公告)日：2024-02-06

申请号：US18156654

申请日：2023-01-19

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Hioka ,  Tsukasa Kobayashi ,  Koji Kato ,  Yuki Shimizu ,  Hiroshi Maejima

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US11763890B2

公开(公告)日：2023-09-19

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

CPC classification number: G11C16/0483 ,  G11C7/109 ,  G11C7/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US12243594B2

公开(公告)日：2025-03-04

申请号：US18476477

申请日：2023-09-28

Applicant: KIOXIA CORPORATION

Inventor： Koji Kato

IPC: G11C5/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

公开(公告)号：US12136458B2

公开(公告)日：2024-11-05

申请号：US17897089

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Tomoki Nakagawa ,  Koji Kato ,  Shuhei Oketa ,  Mai Shimizu

IPC: G11C7/10 ,  G11C16/04 ,  G11C16/08

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

公开(公告)号：US12106808B2

公开(公告)日：2024-10-01

申请号：US18485630

申请日：2023-10-12

Applicant: Kioxia Corporation

Inventor： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

IPC: G11C16/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3427

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US11600328B2

公开(公告)日：2023-03-07

申请号：US17591216

申请日：2022-02-02

Applicant: KIOXIA CORPORATION

Inventor： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US11276466B2

公开(公告)日：2022-03-15

申请号：US16952858

申请日：2020-11-19

Applicant: KIOXIA CORPORATION

Inventor： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US11158385B2

公开(公告)日：2021-10-26

申请号：US16841377

申请日：2020-04-06

Applicant: KIOXIA CORPORATION

Inventor： Koji Kato ,  Hitoshi Shiga

IPC: G11C16/26 ,  H01L27/1157 ,  G11C16/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C8/10 ,  G11C16/10 ,  G11C8/08 ,  G11C16/32 ,  H01L27/11582 ,  G11C16/04

Abstract: A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.

公开(公告)号：US11894074B2

公开(公告)日：2024-02-06

申请号：US17469812

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Koji Kato

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.