公开(公告)号：US20210335433A1

公开(公告)日：2021-10-28

申请号：US17181660

申请日：2021-02-22

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu HARADA ,  Yuji NAGAI ,  Kenro KIKUCHI

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C7/04

Abstract: A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

公开(公告)号：US20250036310A1

公开(公告)日：2025-01-30

申请号：US18779832

申请日：2024-07-22

Applicant: Kioxia Corporation

Inventor： Yoshikazu HARADA ,  Akio SUGAHARA

IPC: G06F3/06 ,  G06F12/0802

Abstract: A semiconductor storage device includes a memory string, a sense amplifier including first and second latch circuits, a cache memory including a third latch circuit, and a control circuit. The control circuit is configured to perform a first read operation in response to a first command set and consecutively perform a second read operation in response to a second command set received during the first read operation. During the first read operation, data read from the memory string is stored in the first latch circuit. When the second command set is received at a first timing, the control circuit transfers the data to the second latch circuit, and then to the third latch circuit. When the second command set is received at a second timing before the first timing, the control circuit directly transfers the data to the third latch circuit.

公开(公告)号：US20240221799A1

公开(公告)日：2024-07-04

申请号：US18609522

申请日：2024-03-19

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C5/02 ,  G11C7/22

CPC classification number: G11C7/1063 ,  G11C5/025 ,  G11C7/222

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20230290390A1

公开(公告)日：2023-09-14

申请号：US18316277

申请日：2023-05-12

Applicant: KIOXIA CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu HARADA ,  Shoichiro HASHIMOTO

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/02

CPC classification number: G11C7/1063 ,  G11C7/222 ,  G11C5/025

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20210334044A1

公开(公告)日：2021-10-28

申请号：US17184674

申请日：2021-02-25

Applicant: Kioxia Corporation

Inventor： Yoshikazu HARADA

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10

Abstract: According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The control circuit is configured to receive a first command set, receive a second command set related to a read operation while rejecting a command set related to a write operation or erase operation in response to the first command set, and execute the read operation on the memory cell array in response to the second command set.