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    Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements
    11.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements 失效
    制造具有单元型非易失性存储元件的半导体集成电路器件的方法

    公开(公告)号：US07399667B2

    公开(公告)日：2008-07-15

    申请号：US11393774

    申请日：2006-03-31

    申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

    摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

    摘要翻译： 一种具有非易失性存储单元的半导体存储器单元，每个非易失性存储单元分别由具有浮置栅极和控制栅极的MISFET形成，以及用作源极和漏极区域的第一和第二半导体区域。 根据其制造方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是具有较低剂量的第二半导体区域，使得形成的第一半导体区域达到结深度 大于第二半导体区域，并且第一和第二半导体区域都具有在浮置栅电极下方延伸的部分。 该装置及其方法的特征还在于外围电路的MISFET的形成。

    Non-volatile semiconductor memory device
    16.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06255690B1

    公开(公告)日：2001-07-03

    申请号：US09282204

    申请日：1999-03-31

    申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    IPC分类号： H01L29788

    CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

    摘要： A semiconductor memory device having nonvolatile memory cells of a single-element type. The nonvolatile memory cells have a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. An impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode.

    摘要翻译： 一种具有单一元件类型的非易失性存储单元的半导体存储器件。 非易失性存储单元通过第二栅极绝缘膜，在半导体衬底的主表面和浮动栅极上的控制栅电极上绝缘地具有浮栅电极。 引入与控制栅电极的一对相对端侧自对准的杂质，以形成第一和第二半导体区域，然而，较低剂量的砷被引入到 第二半导体区域。 根据该方案，第一半导体区域形成为具有大于与第二半导体区域相关联的结深度的结深度，并且第一和第二半导体区域都具有在浮置栅极下方延伸的部分。 此外，存储在浮栅电极中的载流子通过隧穿穿过浮置栅电极下方的绝缘膜而从其转移到第一半导体区域。

    Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements
    17.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements 失效
    制造具有单元型非易失性存储元件的半导体集成电路器件的方法

    公开(公告)号：US5656522A

    公开(公告)日：1997-08-12

    申请号：US451268

    申请日：1995-05-30

    申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    IPC分类号： H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886 ,  G11C16/0416 ,  H01L27/0688

    摘要： A method of manufacturing a semiconductor memory device having non-volatile memory elements or memory cells of a single-element type. The method provides for the formation of a floating gate electrode on a main surface of a semiconductor substrate and a control gate electrode on the floating gate electrode via a second gate insulating film. In accordance with the method, an impurity is introduced in self-alignment with one of a pair of opposing end portions of the control gate electrode to form a first semiconductor region, and on the second of the opposing end portions of the control gate electrode of the memory cell, the same impurity, for example, arsenic, but, however, of a lower dose is introduced in self-alignment to form a second semiconductor region. In accordance with the formation of the first semiconductor region, the impurity is selectively introduced into the substrate by using a mask layer which covers a portion of the main surface of the substrate where the second semiconductor region is to be formed. In accordance with such manufactured memory cells, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region by tunneling through the insulating film underlying the floating gate electrode. The first semiconductor region is formed so as to extend in an overlapping relation with the floating gate electrode by a greater amount than that of the second semiconductor region.

    摘要翻译： 一种制造具有单一元件类型的非易失性存储元件或存储单元的半导体存储器件的方法。 该方法提供了通过第二栅极绝缘膜在半导体衬底的主表面上形成浮置栅电极和浮置栅电极上的控制栅电极。 根据该方法，与控制栅电极的一对相对端部之一自对准地引入杂质以形成第一半导体区域，并且在控制栅电极的相对端部的第二端部 存储单元，相同的杂质，例如砷，但是以较低剂量引入自对准以形成第二半导体区域。 根据第一半导体区域的形成，通过使用覆盖要形成第二半导体区域的基板的主表面的一部分的掩模层，将杂质选择性地引入到基板中。 根据这种制造的存储单元，通过隧穿穿过浮置栅电极下面的绝缘膜，将存储在浮栅中的载流子从其转移到第一半导体区。 第一半导体区域形成为与浮置栅电极重叠地延伸比第二半导体区域大的量。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING SINGLE-ELEMENT TYPE NON-VOLATILE MEMORY ELEMENTS
    18.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING SINGLE-ELEMENT TYPE NON-VOLATILE MEMORY ELEMENTS 审中-公开
    具有单元型非易失性存储器元件的半导体集成电路器件

    公开(公告)号：US20080254582A1

    公开(公告)日：2008-10-16

    申请号：US12138830

    申请日：2008-06-13

    申请人： Kazuhiro KOMORI ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    发明人： Kazuhiro KOMORI ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

    摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

    摘要翻译： 一种具有非易失性存储单元的半导体存储器单元，每个非易失性存储单元分别由具有浮置栅极和控制栅极的MISFET形成，以及用作源极和漏极区域的第一和第二半导体区域。 根据其制造方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是具有较低剂量的第二半导体区域，使得形成的第一半导体区域达到结深度 大于第二半导体区域，并且第一和第二半导体区域都具有在浮置栅电极下方延伸的部分。 该装置及其方法的特征还在于外围电路的MISFET的形成。