公开(公告)号：US20120143379A1

公开(公告)日：2012-06-07

申请号：US13371791

申请日：2012-02-13

Applicant: Kazuhiro Teramoto

Inventor： Kazuhiro Teramoto

IPC: G05D16/20 ,  G08B21/00

CPC classification number: F04B49/02 ,  F04B49/10 ,  F04B2201/0207

Abstract: A control method for an air compressor including a compressor body for compressing air and an item to be replaced used during the operation of the compressor body. The method includes computing a service time of the item to be replaced, being based upon an operating time of the compressor body, discriminating whether the item to be replaced is a manufacturer's recommended item or not, determining whether or not the service time of the item to be replaced discriminated as the manufacturer's recommend item is not longer than a first reference time, but determining whether or not the service time of the item to be replaced discriminated as one which is not the manufacturer's recommended item is not longer than a preset second reference time which is shorter than the first reference time, and issuing an alarm when determining that the reference time is exceeded.

Abstract translation: 一种空气压缩机的控制方法，其包括在压缩机主体的运行期间使用的用于压缩空气的压缩机主体和待更换的物品。 该方法包括：基于压缩机主体的运行时间来计算待更换项目的服务时间，判断要更换的项目是否是制造商的推荐项目，确定项目的服务时间 被替换为被鉴别为制造商的推荐项目不长于第一参考时间，但是确定被替换的项目的服务时间是否被识别为不是制造商的推荐项目的服务时间不长于预设的第二参考 时间短于第一参考时间，并且当确定超过参考时间时发出报警。

公开(公告)号：US20100182862A1

公开(公告)日：2010-07-22

申请号：US12656178

申请日：2010-01-20

Applicant: Kazuhiro Teramoto

Inventor： Kazuhiro Teramoto

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/04 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

Abstract: Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.

Abstract translation: 可以通过在检测到自动刷新命令时基于温度来设定要在一段时间内执行的自动刷新次数来控制半导体器件的自动刷新。

公开(公告)号：US20090016139A1

公开(公告)日：2009-01-15

申请号：US12169873

申请日：2008-07-09

Applicant: Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

Inventor： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C7/08 ,  G11C11/4091

Abstract: A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.

Abstract translation: 提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。 半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

公开(公告)号：US20080112244A1

公开(公告)日：2008-05-15

申请号：US11979954

申请日：2007-11-09

Applicant: Kazuhiro Teramoto ,  Yoji Idei

Inventor： Kazuhiro Teramoto ,  Yoji Idei

IPC: G11C7/00

CPC classification number: G11C7/065 ,  G11C11/4091 ,  G11C2207/065

Abstract: A semiconductor memory device includes a shared transistor controlling coupling between a bit line pair in a memory cell array and a bit line pair in a sense amplifier. After a word line is activated and the sense amplifier amplifies the potential difference between the bit lines of the bit line pair in the sense amplifier, the shared transistor is tuned OFF and precharge/equalizing circuit is activated to precharge the bit lines in the sense amplifier to a potential which is half the internal power source potential.

Abstract translation: 半导体存储器件包括控制存储单元阵列中的位线对与读出放大器中的位线对之间的耦合的共享晶体管。 在字线被激活并且读出放大器放大读出放大器中位线对的位线之间的电位差之后，共享晶体管被调谐为关闭，并且预充电/均衡电路被激活以对读出放大器中的位线进行预充电 达到内部电源电位的一半的电位。

公开(公告)号：US08422327B2

公开(公告)日：2013-04-16

申请号：US12801124

申请日：2010-05-24

Applicant: Kazuhiro Teramoto ,  Hiroki Fujisawa ,  Susumu Takahashi

Inventor： Kazuhiro Teramoto ,  Hiroki Fujisawa ,  Susumu Takahashi

IPC: G11C17/18

CPC classification number: G11C29/02 ,  G11C17/165 ,  G11C29/027 ,  G11C29/785 ,  G11C29/846

Abstract: To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.

Abstract translation: 为了提供一种包括高电平或低电平的一对反熔丝元件的半导体器件，OR电路为至少一个反熔丝元件处于高电平的情况下输出不同的逻辑信息，以及两个 的反熔丝元件为低电平，异或电路输出逻辑状态彼此不同的情况下的不同的逻辑信息以及彼此相同的情况。

公开(公告)号：US20100302833A1

公开(公告)日：2010-12-02

申请号：US12801124

申请日：2010-05-24

Applicant: Kazuhiro Teramoto ,  Hiroki Fujisawa ,  Susumu Takahashi

Inventor： Kazuhiro Teramoto ,  Hiroki Fujisawa ,  Susumu Takahashi

IPC: G11C17/00 ,  G11C29/04

CPC classification number: G11C29/02 ,  G11C17/165 ,  G11C29/027 ,  G11C29/785 ,  G11C29/846

Abstract: To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.

Abstract translation: 为了提供一种包括高电平或低电平的一对反熔丝元件的半导体器件，OR电路为至少一个反熔丝元件处于高电平的情况下输出不同的逻辑信息，以及两个 的反熔丝元件为低电平，异或电路输出逻辑状态彼此不同的情况下的不同的逻辑信息以及彼此相同的情况。

公开(公告)号：US07719911B2

公开(公告)日：2010-05-18

申请号：US12169873

申请日：2008-07-09

Applicant: Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

Inventor： Kazuhiro Teramoto ,  Yoji Idei ,  Takenori Sato ,  Hiroki Fujisawa

IPC: G11C7/00

CPC classification number: G11C5/14 ,  G11C7/08 ,  G11C11/4091

Abstract: A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a signal read from a memory cell; a first power supply line connected to a source terminal of the P-channel MOS transistor provided in each of the sense amplifiers; a second power supply line which supplies an overdrive voltage to the sense amplifiers at a potential higher than a write potential of the memory cell; a third power supply line connected to an external power supply, a connection element which connects and disconnects the first power supply line and the second power supply line; a capacitance element connected to the second power supply line; and a resistance element inserted between the second power supply line and the third power supply line.

Abstract translation: 提供一种半导体存储装置，其能够在低电压和小的装置区域中使用过驱动方法。 半导体器件包括：存储单元; 读出放大器，每个具有P沟道和N沟道MOS晶体管，并放大从存储单元读取的信号; 连接到设置在每个读出放大器中的P沟道MOS晶体管的源极端子的第一电源线; 第二电源线，其以比存储单元的写入电位高的电位向读出放大器提供过驱动电压; 连接到外部电源的第三电源线，连接和断开第一电源线和第二电源线的连接元件; 连接到第二电源线的电容元件; 以及插入在第二电源线和第三电源线之间的电阻元件。

公开(公告)号：US20080116956A1

公开(公告)日：2008-05-22

申请号：US11984464

申请日：2007-11-19

Applicant: Kazuhiro Teramoto ,  Yoji Idei

Inventor： Kazuhiro Teramoto ,  Yoji Idei

IPC: H03K3/01

CPC classification number: H03K3/356113 ,  H03K19/0016 ,  H03K2217/0018

Abstract: A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.

Abstract translation: 半导体器件以活动模式或待机模式工作，并且包括提供在待机模式下比在活动模式中更高的衬底电位的衬底电位电源线以及提供源的源极 - 电位电源线 待机模式下的电位低于活动模式。 在从待机模式切换到激活模式的模式期间，电位均衡晶体管导通以使从衬底电位电源线流到源极电源线的电流通过，以减少移位所需的时间长度 从待机模式到活动模式。

公开(公告)号：US06480053B1

公开(公告)日：2002-11-12

申请号：US09587474

申请日：2000-06-05

Applicant: Kazuhiro Teramoto

Inventor： Kazuhiro Teramoto

IPC: H03K17735

CPC classification number: G11C29/12005 ,  G05F1/465 ,  H03K17/693

Abstract: A plurality of the P-channel transistors of Group A and a plurality of P-channel transistors of Group B are connected between the power-supply-voltage VCC and the ground, and an output signal SUBUP is obtained from the node C via two inverters. Each terminal of. Transistors of Group B is connected to the ground via N-channel first, second and third transistors. The first signals &phgr;1 and &phgr;2 are inputted to the gates of the first and second transistors and the output of the NOR logical circuit is inputted to the gate of the third transistor. Current performance of the P-channel transistors of Group B is adjusted to control the substrate voltage and to make the substrate voltage both higher and lower than that of normal operation by the use of the test modes. So, the substrate voltage can be changed during hold tests in a selection process to accelerate the tests and shorten the selection time.

Abstract translation: 组A的多个P沟道晶体管和组B的多个P沟道晶体管连接在电源电压VCC和地之间，并且通过两个反相器从节点C获得输出信号SUBUP 。 每个终端。 B组的晶体管通过N沟道第一，第二和第三晶体管连接到地。 第一信号phi1和phi2被输入到第一和第二晶体管的栅极，并且NOR逻辑电路的输出被输入到第三晶体管的栅极。 调整组B的P沟道晶体管的当前性能以通过使用测试模式来控制衬底电压并使衬底电压高于和低于正常工作。 因此，可以在选择过程中的保持测试期间改变衬底电压，以加速测试并缩短选择时间。