公开(公告)号：US20070228474A1

公开(公告)日：2007-10-04

申请号：US11512229

申请日：2006-08-30

申请人： Kazutaka Takeuchi

发明人： Kazutaka Takeuchi

IPC分类号： H01L23/62

CPC分类号： H01L29/1087 ,  H01L21/823892 ,  H01L27/0928 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device including a semiconductor substrate and a MOS transistor having a source diffusion region and a drain diffusion region formed in the semiconductor substrate. A well is formed in the semiconductor substrate. A back gate diffusion region is defined in the vicinity of the source diffusion region or the drain diffusion region. The back gate diffusion region is of a conductivity type that is the same as that of the source diffusion region or the drain diffusion region. A potential control layer, arranged in the semiconductor substrate or under the well, controls the potential at the semiconductor substrate or the well.

摘要翻译： 一种半导体集成电路器件，包括半导体衬底和形成在半导体衬底中的源极扩散区和漏极扩散区的MOS晶体管。 在半导体衬底中形成阱。 背栅极扩散区域限定在源极扩散区域或漏极扩散区域附近。 背栅极扩散区域是与源极扩散区域或漏极扩散区域相同的导电类型。 布置在半导体衬底或阱下的电位控制层控制半导体衬底或阱处的电位。

公开(公告)号：US07178116B2

公开(公告)日：2007-02-13

申请号：US10968110

申请日：2004-10-20

申请人： Kazutaka Takeuchi

发明人： Kazutaka Takeuchi

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068

摘要： A method for designing a semiconductor integrated circuit includes performing logic design and physical design. The method estimates whether logic design data generated in the logic design is appropriate for use in the physical design before the physical design is started. The result of the estimation is fed back to the logic design and reflected in the logic design data.

摘要翻译： 一种用于设计半导体集成电路的方法包括执行逻辑设计和物理设计。 该方法估计逻辑设计中生成的逻辑设计数据是否适合在物理设计开始之前在物理设计中使用。 估计的结果反馈到逻辑设计并反映在逻辑设计数据中。

公开(公告)号：US20060005152A1

公开(公告)日：2006-01-05

申请号：US10968110

申请日：2004-10-20

申请人： Kazutaka Takeuchi

发明人： Kazutaka Takeuchi

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068

摘要： A method for designing a semiconductor integrated circuit includes performing logic design and physical design. The method estimates whether logic design data generated in the logic design is appropriate for use in the physical design before the physical design is started. The result of the estimation is fed back to the logic design and reflected in the logic design data.

摘要翻译： 一种用于设计半导体集成电路的方法包括执行逻辑设计和物理设计。 该方法估计逻辑设计中生成的逻辑设计数据是否适合在物理设计开始之前在物理设计中使用。 估计的结果反馈到逻辑设计并反映在逻辑设计数据中。

公开(公告)号：US06453143B2

公开(公告)日：2002-09-17

申请号：US09861675

申请日：2001-05-22

申请人： Kazutaka Takeuchi

发明人： Kazutaka Takeuchi

IPC分类号： G03G1516

CPC分类号： G03G15/1685 ,  G03G15/161 ,  G03G2215/0177

摘要： In a transfer belt, serving as the endless belt, a groove is formed so as to set a side surface of the rib member at a position separated by a distance A from a lateral-direction end of the transfer belt. The distance A is longer than a distance X between a first end and a second end of the rib member.

摘要翻译： 在用作环形带的转印带中，形成凹槽，以将肋构件的侧表面设置在与转印带的横向端部分开距离A的位置处。 距离A比肋构件的第一端和第二端之间的距离X长。

公开(公告)号：US06375358B1

公开(公告)日：2002-04-23

申请号：US09553619

申请日：2000-04-20

申请人： Ichiro Maekawa ,  Kazutaka Takeuchi

发明人： Ichiro Maekawa ,  Kazutaka Takeuchi

IPC分类号： F16C3206

CPC分类号： G02B26/121 ,  F16C17/026 ,  F16C33/107 ,  F16C33/109

摘要： A shaft integral with a rotary polygon mirror is fitted in a sleeve so as to be rotatable, and the bearing clearance is filled with a lubricant. The lubricant comprises a base oil comprising a mixed oil consisting of a plurality of components whose vapor pressures are equal or close to each other. Suitably combining components of different viscosities makes it possible to prepare the lubricant so as to have such a viscosity to match with the bearing characteristics. Selection of components having a little difference in vapor pressure prevents viscosity change due to volatilization of a specific component. Thus, the viscosity change of the lubricant in the bearing clearance is prevented.

摘要翻译： 与旋转多面镜一体的轴装配在套筒中以便可旋转，并且轴承间隙充满润滑剂。 润滑剂包括基础油，其包含由蒸气压相等或相近的多个组分组成的混合油。 适当地组合不同粘度的组分使得可以制备润滑剂以使其具有与轴承特性相匹配的粘度。 选择蒸汽压稍有差异的组分可防止由于特定成分的挥发引起的粘度变化。 因此，防止润滑剂在轴承间隙中的粘度变化。

公开(公告)号：USD277771S

公开(公告)日：1985-02-26

申请号：US446146

申请日：1982-12-02

申请人： Kazutaka Takeuchi

设计人： Kazutaka Takeuchi

公开(公告)号：US08015534B2

公开(公告)日：2011-09-06

申请号：US12252043

申请日：2008-10-15

申请人： Takashi Kurihara ,  Kazutaka Takeuchi

发明人： Takashi Kurihara ,  Kazutaka Takeuchi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： A method, apparatus, and recording medium including computer instructions for estimating the size of a core section of a semiconductor integrated circuit are provided. The method includes calculating a total net length of wires of nets and usable channel length of the core section by referring to circuit information and a layout parameter that are used to design the semiconductor integrated circuit. The method includes determining a size of the core section that satisfies conditions based on total net length and usable channel length.

摘要翻译： 提供了包括用于估计半导体集成电路的芯部的尺寸的计算机指令的方法，装置和记录介质。 该方法包括通过参考用于设计半导体集成电路的电路信息和布局参数来计算网线的总净长度和芯部分的可用信道长度。 该方法包括基于总净长度和可用信道长度来确定满足条件的核心部分的大小。

公开(公告)号：US07454724B2

公开(公告)日：2008-11-18

申请号：US10823649

申请日：2004-04-14

申请人： Takashi Kurihara ,  Kazutaka Takeuchi

发明人： Takashi Kurihara ,  Kazutaka Takeuchi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： A method for accurately determining the provisional quantity and provisional locations of power supply pads prior to detailed layout of a semiconductor integrated circuit. The method decreases redesigning, shortens the design time, and lowers design costs. The method includes performing a power supply network analysis of the core section to obtain voltage values of the nodes, calculating current values between the nodes from the voltage values of the nodes and the resistances between the nodes, and calculating current values of the power supply pads from the current values between the nodes. The method further includes determining whether to eliminate or add a power supply pad depending on whether the current value of each power supply pad exceeds the current capacity of an associated IO buffer.

摘要翻译： 一种用于在半导体集成电路的详细布局之前准确地确定电源焊盘的临时位置和临时位置的方法。 该方法减少了重新设计，缩短了设计时间，降低了设计成本。 该方法包括执行核心部分的电源网络分析以获得节点的电压值，从节点的电压值和节点之间的电阻计算节点之间的电流值，并计算电源焊盘的电流值 从节点之间的当前值。 该方法还包括根据每个电源焊盘的当前值是否超过相关联的IO缓冲器的当前容量来确定是否消除或添加电源焊盘。

公开(公告)号：US06962637B2

公开(公告)日：2005-11-08

申请号：US09934694

申请日：2001-08-23

申请人： Kazutaka Takeuchi ,  Shoichi Shimura

发明人： Kazutaka Takeuchi ,  Shoichi Shimura

IPC分类号： G03G15/20 ,  B29C43/02 ,  B29C53/38 ,  B29C53/40 ,  B29C53/56 ,  B29C65/00 ,  B29C65/02 ,  B29C65/04 ,  B29C65/18 ,  B29L23/00 ,  B32B1/08 ,  B32B31/00

CPC分类号： B29C53/562 ,  B29C53/40 ,  B29C65/18 ,  B29C66/1122 ,  B29C66/1142 ,  B29C66/1162 ,  B29C66/4322 ,  B29C66/4329 ,  B29C66/49 ,  B29C66/73161 ,  B29C66/8122 ,  B29C66/81241 ,  B29C66/81261 ,  B29C66/8284 ,  B29L2023/22 ,  Y10T156/1038 ,  Y10T428/1393 ,  B29K2907/04

摘要： A method of manufacturing a tubular film includes the steps of: winding a thermoplastic sheet film on a columnar member with at least two turns so that leading and trailing ends of the film are placed approximately on one normal line of an outer surface of the columnar member without overlapping each other; fitting a tubular molding member on the wound film; and connecting the leading and trailing ends of the film by heating at least the film, thereby forming the sheet film into the tubular film. The resulting tubular film has a high film thickness uniformity and suitable for a fixing film of an image forming apparatus.

摘要翻译： 一种制造管状膜的方法包括以下步骤：将至少两匝的热塑性薄膜卷绕在柱状构件上，使得薄膜的前端和后端大致放置在柱状构件的外表面的一条法线上 不重叠; 将管状模制件装配在卷绕膜上; 并且通过至少加热所述薄膜来连接薄膜的前端和后端，由此将薄膜形成管状薄膜。 所得到的管状膜具有高的膜厚度均匀性并且适用于图像形成装置的定影膜。

公开(公告)号：US20050050502A1

公开(公告)日：2005-03-03

申请号：US10823649

申请日：2004-04-14

申请人： Takashi Kurihara ,  Kazutaka Takeuchi

发明人： Takashi Kurihara ,  Kazutaka Takeuchi

IPC分类号： G06F17/50 ,  G06F9/45 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： A method for accurately determining the provisional quantity and provisional locations of power supply pads prior to detailed layout of a semiconductor integrated circuit. The method decreases redesigning, shortens the design time, and lowers design costs. The method includes performing a power supply network analysis of the core section to obtain voltage values of the nodes, calculating current values between the nodes from the voltage values of the nodes and the resistances between the nodes, and calculating current values of the power supply pads from the current values between the nodes. The method further includes determining whether to eliminate or add a power supply pad depending on whether the current value of each power supply pad exceeds the current capacity of an associated IO buffer.

摘要翻译： 一种用于在半导体集成电路的详细布局之前准确地确定电源焊盘的临时位置和临时位置的方法。 该方法减少了重新设计，缩短了设计时间，降低了设计成本。 该方法包括执行核心部分的电源网络分析以获得节点的电压值，从节点的电压值和节点之间的电阻计算节点之间的电流值，并计算电源焊盘的电流值 从节点之间的当前值。 该方法还包括根据每个电源焊盘的当前值是否超过相关联的IO缓冲器的当前容量来确定是否消除或添加电源焊盘。