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    Multicore Processor Having Storage for Core-Specific Operational Data
    11.
    发明申请
    Multicore Processor Having Storage for Core-Specific Operational Data 有权
    具有存储核心特定操作数据的多核处理器

    公开(公告)号：US20090055826A1

    公开(公告)日：2009-02-26

    申请号：US11842206

    申请日：2007-08-21

    申请人： Kerry Bernstein ,  Nazmul Habib ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Nazmul Habib ,  Norman J. Rohrer

    IPC分类号： G06F9/46 ,  G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/3891

    摘要： An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data processing system, where the method includes providing a multicore processor that contains a plurality of processor cores and a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency for each of the plurality of processor cores. The method further includes operating a scheduler coupled to an operating system and to the multicore processor, where the scheduler is operated to be responsive at least in part to information read from the memory to schedule the execution of threads to individual ones of the processor cores for a more optimal usage of energy.

    摘要翻译： 集成电路包括多个处理器核心和可读非易失性存储器，其存储表示多个处理器核心中的每一个的至少一个操作特性的信息。 还公开了一种操作数据处理系统的方法，其中所述方法包括提供包含多个处理器核心的多核处理器和存储在测试操作期间确定的信息的可读非易失性存储器，其指示至少 用于所述多个处理器核心中的每一个的最大工作频率。 所述方法还包括操作耦合到操作系统和多核处理器的调度器，其中调度器被操作以至少部分地响应于从存储器读取的信息，以调度到处理器核心中的各个处理器核心的线程的执行 更优化的能量使用。

    Low leakage monotonic CMOS logic
    12.
    发明授权
    Low leakage monotonic CMOS logic 有权
    低泄漏单调CMOS逻辑

    公开(公告)号：US07084667B2

    公开(公告)日：2006-08-01

    申请号：US10710453

    申请日：2004-07-13

    申请人： Kerry Bernstein ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Norman J. Rohrer

    IPC分类号： H03K19/0175

    CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

    摘要： A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

    摘要翻译： 低泄漏单调CMOS逻辑电路及其设计方法，设计方法及设计方法。 该电路包括：一个或多个逻辑级，逻辑级中的至少一个具有主要高输入状态或具有主要低输入状态; 其中具有主要高输入状态的逻辑级包括相对于参考PFET和相对于参考NFET的一个或多个厚栅极电介质和低阈值电压NFET的一个或多个薄栅极电介质和高阈值电压PFET; 并且其中具有主要为低输入状态的逻辑级包括相对于参考PFET和相对于参考NFET的一个或多个薄栅极电介质和高阈值电压NFET的一个或多个厚栅极电介质和低阈值电压PFET。

    Methodology for fixing Qcrit at design timing impact
    13.
    发明授权
    Methodology for fixing Qcrit at design timing impact 失效
    在设计时间上影响Qcrit的方法

    公开(公告)号：US06954916B2

    公开(公告)日：2005-10-11

    申请号：US10604179

    申请日：2003-06-30

    申请人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  Leendert M. Huisman ,  Paul D. Kartschoke ,  Norman J. Rohrer

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5022

    摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.

    摘要翻译： 一种用于模拟集成电路的方法和系统。 该方法包括以下步骤：执行电路的定时分析，以确保它们满足规定的时序准则，执行电路的软错误分析，以确定它们是否符合指定的软错误标准，以及改进那些无法通过软错误分析的电路 提高其对软错误的抵抗力，并且在时序上没有劣化。 优选地，改进步骤包括通过具有附加电压源或改变电路的电容来改进不能通过软误差分析的那些电路的步骤。

    DTCMOS circuit having improved speed
    14.
    发明授权
    DTCMOS circuit having improved speed 失效
    DTCMOS电路具有改进的速度

    公开(公告)号：US06326666B1

    公开(公告)日：2001-12-04

    申请号：US09534902

    申请日：2000-03-23

    申请人： Kerry Bernstein ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Norman J. Rohrer

    IPC分类号： H01L2701

    CPC分类号： H01L27/1203

    摘要： A DTCMOS circuit produces an output based on a logical combination of input logic signals. The circuit includes input transistors which receive on a respective gate a respective logic signal. The transistors have a body contact which is connected to the gate of another transistor. Transistors which are receiving later arriving logic signals therefore have a threshold voltage lowered by an earlier arriving logic signal. By coupling the earlier arriving logic signal with a body contact of another input transistor, the threshold voltage may be lowered prior to processing of the subsequently arriving logic signal. The DTCMOS circuit may be implemented in SOI with the attendant benefits of a lower supply made possible by the lowered voltage threshold each of the transistors without sacrificing leakage current inherent in DTCMOS circuits.

    摘要翻译： DTCMOS电路基于输入逻辑信号的逻辑组合产生输出。 电路包括输入晶体管，其在相应的栅极上接收相应的逻辑信号。 晶体管具有连接到另一个晶体管的栅极的体接触。 因此，接收稍后到达的逻辑信号的晶体管具有由较早到达的逻辑信号降低的阈值电压。 通过将先前到达的逻辑信号与另一个输入晶体管的体接触耦合，在处理随后到达的逻辑信号之前可以降低阈值电压。 DTCMOS电路可以在SOI中实施，并且由于每个晶体管的降低的电压阈值可能降低电源所带来的好处，而不会牺牲DTCMOS电路固有的漏电流。

    ERROR CORRECTING LOGIC SYSTEM
    15.
    发明申请
    ERROR CORRECTING LOGIC SYSTEM 有权
    错误修正逻辑系统

    公开(公告)号：US20090002015A1

    公开(公告)日：2009-01-01

    申请号：US11850857

    申请日：2007-09-06

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/003

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

    Error correcting logic system
    16.
    发明授权
    Error correcting logic system 有权
    错误校正逻辑系统

    公开(公告)号：US07471115B2

    公开(公告)日：2008-12-30

    申请号：US11926386

    申请日：2007-10-29

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/096 ,  H03K19/094

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。

    System and method for designing a low leakage monotonic CMOS logic circuit
    17.
    发明授权
    System and method for designing a low leakage monotonic CMOS logic circuit 有权
    用于设计低泄漏单调CMOS逻辑电路的系统和方法

    公开(公告)号：US07389478B2

    公开(公告)日：2008-06-17

    申请号：US11407176

    申请日：2006-04-19

    申请人： Kerry Bernstein ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Norman J. Rohrer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

    摘要： A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

    摘要翻译： 低泄漏单调CMOS逻辑电路及其设计方法，设计方法及设计方法。 该电路包括：一个或多个逻辑级，逻辑级中的至少一个具有主要高输入状态或具有主要低输入状态; 其中具有主要高输入状态的逻辑级包括相对于参考PFET和相对于参考NFET的一个或多个厚栅极电介质和低阈值电压NFET的一个或多个薄栅极电介质和高阈值电压PFET; 并且其中具有主要为低输入状态的逻辑级包括相对于参考PFET和相对于参考NFET的一个或多个薄栅极电介质和高阈值电压NFET的一个或多个厚栅极电介质和低阈值电压PFET。

    SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT
    19.
    发明申请
    SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT 有权
    用于设计低漏电单声道CMOS逻辑电路的系统和方法

    公开(公告)号：US20080195987A1

    公开(公告)日：2008-08-14

    申请号：US12103038

    申请日：2008-04-15

    申请人： Kerry Bernstein ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Norman J. Rohrer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

    摘要： A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.

    摘要翻译： 一种用于设计低泄漏单调CMOS逻辑电路的计算机系统。 执行计算机的系统实现以下步骤：（a）指定具有其阈值电压及其栅介质厚度的参考PFET和具有其阈值电压及其栅介质厚度的参考NFET; （b）用标准设计元件合成示意电路设计，标准设计元件包括一个或多个参考PFET和一个或多个参考NFET; （c）分析具有主要为高输入逻辑状态或主要为低输入逻辑状态的逻辑级的一个或多个电路; （d）选择确定为具有主要高输入逻辑状态或主要为低输入逻辑状态的一个或多个逻辑级; 和（e）用减少的电流泄漏元件代替所选逻辑级的标准设计元件。