公开(公告)号：US07716453B2

公开(公告)日：2010-05-11

申请号：US11575001

申请日：2004-09-10

申请人： Moshe Anschel ,  Moshe Bachar ,  Uri Dayan ,  Jacob Efrat ,  Itay Peled ,  Zvika Rozenshein

发明人： Moshe Anschel ,  Moshe Bachar ,  Uri Dayan ,  Jacob Efrat ,  Itay Peled ,  Zvika Rozenshein

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/1483 ,  G06F12/1491

摘要： A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch. A method for memory management, the method includes: (i) providing multiple data segment descriptors; each data segment descriptor associated with a data memory segment, and providing multiple program segment descriptors, each program segment descriptor associated with a program memory segment; (ii) receiving and storing a program task identifier and a data task identifier; (iii) receiving a data access request and determining how to handle the data access request in response to a content of the multiple data segment descriptors; and (iv) receiving a program access request and determining how to handle the program access request in response to a content of the multiple program segment descriptors.

摘要翻译： 一种存储器管理单元，包括：（i）多个数据段描述符，每个数据段描述符与数据存储段相关联; （ii）多个节目段描述符，每个节目段描述符与节目存储段相关联; 以及（iii）控制器，适于响应于任务切换来替换所述多个数据段描述符和所述多个程序段描述符的内容。 一种用于存储器管理的方法，所述方法包括：（i）提供多个数据段描述符; 每个数据段描述符与数据存储器段相关联，并且提供多个程序段描述符，每个程序段描述符与程序存储段相关联; （ii）接收和存储程序任务标识符和数据任务标识符; （iii）响应于所述多个数据段描述符的内容，接收数据访问请求并确定如何处理所述数据访问请求; 以及（iv）接收程序访问请求并且响应于所述多个节目段描述符的内容来确定如何处理所述节目访问请求。

公开(公告)号：US20070277009A1

公开(公告)日：2007-11-29

申请号：US11575001

申请日：2004-09-10

申请人： Moshe Anschel ,  Moshe Bachar ,  Uri Dayan ,  Jacob Efrat ,  Itay Peled ,  Zvika Rozenshein

发明人： Moshe Anschel ,  Moshe Bachar ,  Uri Dayan ,  Jacob Efrat ,  Itay Peled ,  Zvika Rozenshein

IPC分类号： G06F13/00

CPC分类号： G06F12/1036 ,  G06F12/1483 ,  G06F12/1491

摘要： A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch. A method for memory management, the method includes: (i) providing multiple data segment descriptors; each data segment descriptor associated with a data memory segment, and providing multiple program segment descriptors, each program segment descriptor associated with a program memory segment; (ii) receiving and storing a program task identifier and a data task identifier; (iii) receiving a data access request and determining how to handle the data access request in response to a content of the multiple data segment descriptors; and (iv) receiving a program access request and determining how to handle the program access request in response to a content of the multiple program segment descriptors.

摘要翻译： 一种存储器管理单元，包括：（i）多个数据段描述符，每个数据段描述符与数据存储段相关联; （ii）多个节目段描述符，每个节目段描述符与节目存储段相关联; 以及（iii）控制器，适于响应于任务切换来替换所述多个数据段描述符和所述多个程序段描述符的内容。 一种用于存储器管理的方法，所述方法包括：（i）提供多个数据段描述符; 每个数据段描述符与数据存储器段相关联，并且提供多个程序段描述符，每个程序段描述符与程序存储段相关联; （ii）接收和存储程序任务标识符和数据任务标识符; （iii）响应于所述多个数据段描述符的内容，接收数据访问请求并确定如何处理所述数据访问请求; 以及（iv）接收程序访问请求并且响应于所述多个节目段描述符的内容来确定如何处理所述节目访问请求。

公开(公告)号：US08281080B2

公开(公告)日：2012-10-02

申请号：US10933191

申请日：2004-09-02

申请人： Kostantin Godin ,  Moshe Anschel ,  Uri Dayan ,  Dvir Rune R Peleg

发明人： Kostantin Godin ,  Moshe Anschel ,  Uri Dayan ,  Dvir Rune R Peleg

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F9/526

摘要： A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information unit over the first bus; (iii) attempting to complete the snooping type atomic operation of an updated information unit; and (iv) defining the atomic operation as a failed atomic operation if during at least one stage of receiving, providing and attempting, the first address was locked as a result of a locking type atomic operation.

摘要翻译： 一种用于修改信息单元的系统和方法，所述方法包括以下阶段：（i）通过第一总线接收发起与位于第一总线的第一地址处的至少一个信息单元相关联的窥探型原子操作的请求 内存模块; （ii）通过第一个总线提供信息单元; （iii）尝试完成更新的信息单元的窥探型原子操作; 以及（iv）如果在接收，提供和尝试的至少一个阶段中将第一地址作为锁定型原子操作的结果锁定，则将原子操作定义为失败的原子操作。

公开(公告)号：US09436624B2

公开(公告)日：2016-09-06

申请号：US13952092

申请日：2013-07-26

申请人： Ziv Zamsky ,  Moshe Anschel ,  Itay Keidar ,  Itay S. Peled ,  Doron Schupper ,  Yakov Tokar

发明人： Ziv Zamsky ,  Moshe Anschel ,  Itay Keidar ,  Itay S. Peled ,  Doron Schupper ,  Yakov Tokar

IPC分类号： G06F13/14 ,  G06F3/00 ,  G06F13/16

CPC分类号： G06F13/16

摘要： A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.

摘要翻译： 一种用于计算系统的电路，包括第一加载/存储单元，LSU和第二LSU以及存储器装置。 第一LSU经由包括第一写总线和第一读总线的第一总线装置连接到存储器装置。 第二LSU经由包括第二写总线和第二读总线的第二总线装置连接到存储器装置。 计算系统被配置为执行多重加载指令以经由第一读取总线和第二读取总线读取数据和/或执行多个存储指令以经由第一写入总线和第二写入总线写入数据。

公开(公告)号：US08095769B2

公开(公告)日：2012-01-10

申请号：US12194273

申请日：2008-08-19

申请人： Rotem Porat ,  Moshe Anschel ,  Itay Peled ,  Erez Steinberg ,  Ziv Zamsky

发明人： Rotem Porat ,  Moshe Anschel ,  Itay Peled ,  Erez Steinberg ,  Ziv Zamsky

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F12/0292 ,  G06F12/1441 ,  Y02D10/13

摘要： A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.

摘要翻译： 一种用于地址比较的方法，所述方法包括：（i）接收输入地址; （ii）并行地将所述组的每个存储器段的输入地址与存储器段边界进行比较来确定所述输入地址是否在一组存储器段内的存储器段内; （iii）其中输入地址和存储器段边界之间的比较包括：（a）对输入地址的最高有效部分的比特和存储器段边界的最高有效部分的相应比特应用异或运算; （b）忽略输入地址的最低有效部分的位和存储器段边界的最低有效部分的对应位; 以及（c）通过利用一组全比较器比较输入地址的中间部分的位与存储器段边界的中间部分的相应位之间的比较; 其中响应于对所述存储器段施加的对准限制而选择形成所述输入地址和所述存储器段边界的中间部分的位的位置，以及对所述存储器段的大小以及响应于对所述存储器段边界施加的边界限制 内存段。

公开(公告)号：US20100049939A1

公开(公告)日：2010-02-25

申请号：US12194273

申请日：2008-08-19

申请人： Rotem Porat ,  Moshe Anschel ,  Itay Peled ,  Erez Steinberg ,  Ziv Zamsky

发明人： Rotem Porat ,  Moshe Anschel ,  Itay Peled ,  Erez Steinberg ,  Ziv Zamsky

IPC分类号： G06F12/02

CPC分类号： G06F12/0292 ,  G06F12/1441 ,  Y02D10/13

摘要： A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.

摘要翻译： 一种用于地址比较的方法，所述方法包括：（i）接收输入地址; （ii）并行地将所述组的每个存储器段的输入地址与存储器段边界进行比较来确定所述输入地址是否在一组存储器段内的存储器段内; （iii）其中输入地址和存储器段边界之间的比较包括：（a）对输入地址的最高有效部分的比特和存储器段边界的最高有效部分的相应比特应用异或运算; （b）忽略输入地址的最低有效部分的位和存储器段边界的最低有效部分的对应位; 以及（c）通过利用一组全比较器比较输入地址的中间部分的位与存储器段边界的中间部分的相应位之间的比较; 其中响应于对所述存储器段施加的对准限制而选择形成所述输入地址和所述存储器段边界的中间部分的位的位置，以及对所述存储器段的大小以及响应于对所述存储器段边界施加的边界限制 内存段。

公开(公告)号：US20060059312A1

公开(公告)日：2006-03-16

申请号：US10940121

申请日：2004-09-14

申请人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

发明人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F12/0862

摘要： A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.

摘要翻译： 一种用于响应于危险指示信息获取信息的方法，所述方法包括：（i）将危险指示信息与被提取到所述缓存模块的至少一个信息单元相关联; （ii）接收执行取出操作的请求; 以及（iii）响应于所述危险指示信息以及响应于与所述至少一个信息单元相关联的脏信息，确定是否将至少一个信息单元提取给所述高速缓存模块。

公开(公告)号：US20080301371A1

公开(公告)日：2008-12-04

申请号：US11570303

申请日：2005-05-31

申请人： Itay Peled ,  Moshe Anschel ,  Yacov Efrat ,  Alon Eldar

发明人： Itay Peled ,  Moshe Anschel ,  Yacov Efrat ,  Alon Eldar

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F12/0842 ,  G06F12/0891

摘要： A memory cache control arrangement for performing a coherency operation on a memory cache comprises a receive processor for receiving an address group indication for an address group comprising a plurality of addresses associated with a main memory. The address group indication may indicate a task identity and an address range corresponding to a memory block of the main memory. A control unit processes each line of a group of cache lines sequentially. Specifically it is determined if each cache line is associated with an address of the address group by evaluating a match criterion. If the match criterion is met, a coherency operation is performed on the cache line. If a conflict exists between the coherency operation and another memory operation the coherency means inhibits the coherency operation. The invention allows a reduced duration of a cache coherency operation. The duration is further independent of the size of the main memory address space covered by the coherency operation.

摘要翻译： 一种用于在存储器高速缓存中执行一致性操作的存储器高速缓存控制装置，包括接收处理器，用于接收包括与主存储器相关联的多个地址的地址组的地址组指示。 地址组指示可以指示对应于主存储器的存储块的任务标识和地址范围。 控制单元依次处理一组高速缓存行的每一行。 具体地说，通过评估匹配标准来确定每个高速缓存行是否与地址组的地址相关联。 如果满足匹配条件，则在高速缓存行上执行一致性操作。 如果在一致性操作和另一个存储器操作之间存在冲突，则相关性意味着禁止一致性操作。 本发明允许缓存一致性操作的持续时间缩短。 持续时间进一步与由一致性操作覆盖的主存储器地址空间的大小无关。

公开(公告)号：US08458407B2

公开(公告)日：2013-06-04

申请号：US12530575

申请日：2007-03-13

申请人： Rotem Porat ,  Moshe Anschel ,  Shai Koren ,  Itay Peled ,  Erez Steinberg

发明人： Rotem Porat ,  Moshe Anschel ,  Shai Koren ,  Itay Peled ,  Erez Steinberg

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

摘要翻译： 一种用于产生高速缓存用户发起的预取请求的方法，所述方法包括发起用户发起的预取请求的序列; 该方法的特征在于：响应于：最后触发事件的发生的定时，用户发起的预取序列延迟周期来确定用户发起的预取请求序列的用户发起的预取请求的定时 和用户启动的预取序列速率。

公开(公告)号：US20100122037A1

公开(公告)日：2010-05-13

申请号：US12530575

申请日：2007-03-13

申请人： Rotem Porat ,  Moshe Anschel ,  Shai Koren ,  Itay Peled ,  Erez Steinberg

发明人： Rotem Porat ,  Moshe Anschel ,  Shai Koren ,  Itay Peled ,  Erez Steinberg

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862

摘要： A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

摘要翻译： 一种用于产生高速缓存用户发起的预取请求的方法，所述方法包括发起用户发起的预取请求的序列; 该方法的特征在于：响应于：最后触发事件的发生的定时，用户发起的预取序列延迟周期来确定用户发起的预取请求序列的用户发起的预取请求的定时 和用户启动的预取序列速率。