公开(公告)号：US07225393B2

公开(公告)日：2007-05-29

申请号：US10673255

申请日：2003-09-30

申请人： Takehiro Kamada

发明人： Takehiro Kamada

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/25 ,  H03M13/41 ,  H03M13/4169

摘要： In the Viterbi decoder for decoding a trellis-coded modulated signal of this invention, a path memory is constructed of a general RAM, whereby the circuit size and power consumption are reduced. A trace-back section traces back path select signals stored in a trace-back memory by a predetermined length. Using the number of a node through which a most likely path passes obtained by the tracing back and in accordance with a trellis diagram, a subset number generator section outputs coding bits relating to transition to the node concerned and a subset number. A selector section selectively outputs a noncoding bit relating to the transition to the node based on the subset number.

摘要翻译： 在用于解码本发明的网格编码调制信号的维特比解码器中，路径存储器由通用RAM构成，从而降低了电路尺寸和功耗。 追溯部分将存储在追溯存储器中的路径选择信号追溯到预定长度。 使用通过跟踪获得的最可能的路径通过的节点的数量，并且根据网格图，子集编号生成器部分输出与所涉及的节点的转换相关的编码比特和子集号。 选择器部分基于子集号有选择地输出与转移相关的非编码位。

公开(公告)号：US20050174929A1

公开(公告)日：2005-08-11

申请号：US10514818

申请日：2003-05-16

申请人： Takaya Hayashi ,  Kenichiro Hayashi ,  Takehiro Kamada

发明人： Takaya Hayashi ,  Kenichiro Hayashi ,  Takehiro Kamada

IPC分类号： H04L25/02 ,  H04L25/03 ,  H04J11/00

CPC分类号： H04L25/0222 ,  H04L5/0048 ,  H04L25/022 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2647

摘要： A reception apparatus for receiving an OFDM signal having a plurality of pilot carriers that transmit predetermined pilot signals at predetermined symbols. The reception apparatus transforms the received OFDM signal to a frequency-domain OFDM signal, determines channel responses corresponding to the transmitted pilot signals for each of the pilot carriers among a plurality of carriers constituting the frequency-domain OFDM signal, determines, based on channel responses corresponding to first, second and third pilot signals transmitted sequentially in a same carrier, a channel response at a symbol between the second pilot signal and the third pilot signal, compensates a waveform distortion in the frequency-domain OFDM signal according to the channel response at the symbol between the second pilot signal and the third pilot signal and outputs the results.

摘要翻译： 一种用于接收具有以预定符号发送预定导频信号的多个导频载波的OFDM信号的接收装置。 接收装置将接收的OFDM信号变换为频域OFDM信号，根据信道响应确定构成频域OFDM信号的多个载波中的每个导频载波对应于所发送的导频信号的信道响应 对应于在相同载波中顺序发送的第一，第二和第三导频信号，在第二导频信号和第三导频信号之间的符号处的信道响应，根据信道响应在频域OFDM信号中补偿波形失真 第二导频信号和第三导频信号之间的符号，并输出结果。

公开(公告)号：US06654929B1

公开(公告)日：2003-11-25

申请号：US09672904

申请日：2000-09-29

申请人： Takehiro Kamada

发明人： Takehiro Kamada

IPC分类号： H03M1303

CPC分类号： H03M13/6502 ,  H03M13/25 ,  H03M13/4169 ,  H03M13/6505

摘要： In the Viterbi decoder for decoding a trellis-coded modulated signal of this invention, a path memory is constructed of a general RAM, whereby the circuit size and power consumption are reduced. A trace-back section traces back path select signals stored in a trace-back memory by a predetermined length. Using the number of a node through which a most likely path passes obtained by the tracing back and in accordance with a trellis diagram, a subset number generator section outputs coding bits relating to transition to the node concerned and a subset number. A selector section selectively outputs a noncoding bit relating to the transition to the node based on the subset number.

摘要翻译： 在用于解码本发明的网格编码调制信号的维特比解码器中，路径存储器由通用RAM构成，从而降低了电路尺寸和功耗。 追溯部分将存储在追溯存储器中的路径选择信号追溯到预定长度。 使用通过跟踪获得的最可能的路径通过的节点的数量，并且根据网格图，子集编号生成器部分输出与所涉及的节点的转换相关的编码比特和子集号。 选择器部分基于子集号有选择地输出与转移相关的非编码位。

公开(公告)号：US06263473B1

公开(公告)日：2001-07-17

申请号：US09494362

申请日：2000-01-31

申请人： Takehiro Kamada

发明人： Takehiro Kamada

IPC分类号： H03M1341

CPC分类号： H03M13/6502 ,  H03M13/41 ,  H03M13/4169 ,  H03M13/6505 ,  H03M13/6563

摘要： The present invention provides an improved Viterbi decoder with a trace-back memory that requires a much less storage capacity required for signal decoding processing as compared with a commonly-used trace-back memory. Based on an input received code, an add-compare-select (ACS) circuit generates path select (PS) signals, and m generated PS signals per unit are written into a path storing means and are fed to a starting node number deciding circuit where the number m indicates a trace-back length. The starting node number deciding circuit finds from the m PS signals a trace-back starting node number for a PS signal preceding the m PS signals. PS signals are read out from the path storing means, trace-back processing starts from the starting node number found by the starting node number deciding circuit, and signal decoding processing is carried out. This eliminates the need for providing a state of performing provisional trace-back processing for finding a starting node number, thereby reducing the number of states necessary for the decoding of signals from four down to three. This reduces the storage capacity of memory required for storing PS signals and thereby achieves a considerable reduction of the circuit size.

摘要翻译： 本发明提供了一种具有追溯存储器的改进的维特比解码器，其与常用的追溯存储器相比需要比信号解码处理所需的更少的存储容量。 基于输入接收的代码，加法比较选择（ACS）电路产生路径选择（PS）信号，并且每单位的m个生成的PS信号被写入路径存储装置，并被馈送到起始节点号决定电路， 数字m表示追溯长度。 起始节点号决定电路从m PS信号中找出用于m PS信号之前的PS信号的追溯起始节点号。 从路径存储装置读出PS信号，从起始节点号决定电路所发现的起始节点编号开始追踪处理，进行信号解码处理。 这消除了提供执行用于查找起始节点号码的临时追溯处理的状态的需要，从而减少了信号从4个到3个解码所需的状态数量。 这降低了存储PS信号所需的存储器的存储容量，从而实现了电路尺寸的显着降低。