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公开(公告)号：US20090201064A1
公开(公告)日：2009-08-13
申请号：US12028973
申请日：2008-02-11
IPC分类号： H03K3/00
CPC分类号： H03K5/15026 , H03B27/00 , H03H7/21 , H03H11/22 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03K2005/00293
摘要： A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.
摘要翻译： 公开了可以包括提供时钟信号的时钟以及与时钟通信以调节时钟信号的强度的控制部分的相位内插器系统。 该系统还可以包括发电机电路，以根据从控制部分接收的时钟信号的强度来产生替代时钟信号。
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公开(公告)号：US20110199843A1
公开(公告)日：2011-08-18
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US08284621B2
公开(公告)日：2012-10-09
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C8/18
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US08493801B2
公开(公告)日：2013-07-23
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US20120300564A1
公开(公告)日：2012-11-29
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US07890676B2
公开(公告)日：2011-02-15
申请号：US12185533
申请日：2008-08-04
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器的存储器系统; 出站链路，连接到出站链路的存储器控制器，出站链路包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器设备的多个导电路径; 以及第一存储器层中的至少两个存储器缓冲器件，所述第一存储器层中的每个存储器缓冲器件连接到所述出站链路以从所述存储器控制器接收存储器信号。
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公开(公告)号：US20080301337A1
公开(公告)日：2008-12-04
申请号：US12185533
申请日：2008-08-04
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器的存储器系统; 出站链路，连接到出站链路的存储器控制器，出站链路包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器设备的多个导电路径; 以及第一存储器层中的至少两个存储器缓冲器件，所述第一存储器层中的每个存储器缓冲器件连接到所述出站链路以从所述存储器控制器接收存储器信号。
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公开(公告)号：US07612621B2
公开(公告)日：2009-11-03
申请号：US11749409
申请日：2007-05-16
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
IPC分类号： H03B27/00
CPC分类号： H03K5/151 , H03K5/13 , H03K2005/00052 , H03K2005/00234
摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.
摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。
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公开(公告)号：US08004335B2
公开(公告)日：2011-08-23
申请号：US12028973
申请日：2008-02-11
IPC分类号： H03H11/16
CPC分类号： H03K5/15026 , H03B27/00 , H03H7/21 , H03H11/22 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03K2005/00293
摘要： A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.
摘要翻译： 公开了可以包括提供时钟信号的时钟以及与时钟通信以调节时钟信号的强度的控制部分的相位内插器系统。 该系统还可以包括发电机电路，以根据从控制部分接收的时钟信号的强度来产生替代时钟信号。
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公开(公告)号：US20080285697A1
公开(公告)日：2008-11-20
申请号：US11749409
申请日：2007-05-16
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
IPC分类号： H03D3/24
CPC分类号： H03K5/151 , H03K5/13 , H03K2005/00052 , H03K2005/00234
摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.
摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。
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