公开(公告)号：US08543950B2

公开(公告)日：2013-09-24

申请号：US13490721

申请日：2012-06-07

申请人： Laung-Terng (L.-T.) Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-Po Wang

发明人： Laung-Terng (L.-T.) Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-Po Wang

IPC分类号： G06F17/50 ,  G06F11/00 ,  G01R31/28

CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

公开(公告)号：US20090037786A1

公开(公告)日：2009-02-05

申请号：US12285225

申请日：2008-09-30

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US07779323B2

公开(公告)日：2010-08-17

申请号：US12222931

申请日：2008-08-20

申请人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

发明人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有 多个扫描单元。 该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列 捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。 进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

公开(公告)号：US06957403B2

公开(公告)日：2005-10-18

申请号：US10108238

申请日：2002-03-28

申请人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

发明人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50 ,  G06F19/00

CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

摘要翻译： 一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。 该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。 该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤 和冲洗/随机测试台生成。 此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。 本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

公开(公告)号：US07058869B2

公开(公告)日：2006-06-06

申请号：US10762571

申请日：2004-01-23

申请人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

发明人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318572 ,  G01R31/31705 ,  G01R31/318591

摘要： A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller 301, output-mask network 304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.

摘要翻译： 一种用于基于扫描的集成电路的调试，诊断和/或产量改进的方法和装置，其中嵌入在扫描核心303中的扫描链没有外部访问，例如当它们被图案发生器302和模式压缩器包围时的情况 305，使用DFT（设计为测试）技术，如Logic BIST（内置自检）或压缩扫描。 本发明包括一个输出屏蔽控制器301和一个输出屏蔽网络304，以允许设计者掩蔽所选择的扫描单元311在选定的模式压实器305中被压缩。 本发明还包括输入链掩模控制器和输入掩模网络，用于将恒定逻辑值驱动到所选扫描链的扫描链输入中，以允许设计者从扫描链保持时间违规恢复。 然后提出了计算机辅助设计（CAD）方法来自动合成输出掩模控制器301，输出掩模网络304，输入链掩模控制器和输入掩模网络，并根据合成的扫描 - 基于集成电路。

公开(公告)号：US20060206771A1

公开(公告)日：2006-09-14

申请号：US11164586

申请日：2005-11-29

申请人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

发明人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

IPC分类号： G01R31/28

CPC分类号： G11C29/40 ,  G11C17/14 ,  G11C2029/0405

摘要： A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

摘要翻译： 公开了一种用于控制ROM的操作的只读存储器（ROM）和相关方法。 ROM的内置自检（BIST）电路根据存储在ROM的存储单元的验证区域中的验证数据来验证存储在ROM的多个存储单元的系统区域中的系统数据。

公开(公告)号：US07441165B2

公开(公告)日：2008-10-21

申请号：US11164586

申请日：2005-11-29

申请人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

发明人： Tsai-Wang Tseng ,  Shih-Chia Kao ,  Shing-Wu Tung

IPC分类号： G11C29/00

CPC分类号： G11C29/40 ,  G11C17/14 ,  G11C2029/0405

摘要： A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

摘要翻译： 公开了一种用于控制ROM的操作的只读存储器（ROM）和相关方法。 ROM的内置自检（BIST）电路根据存储在ROM的存储单元的验证区域中的验证数据来验证存储在ROM的多个存储单元的系统区域中的系统数据。