公开(公告)号：US08543950B2

公开(公告)日：2013-09-24

申请号：US13490721

申请日：2012-06-07

申请人： Laung-Terng (L.-T.) Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-Po Wang

发明人： Laung-Terng (L.-T.) Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-Po Wang

IPC分类号： G06F17/50 ,  G06F11/00 ,  G01R31/28

CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

公开(公告)号：US07444567B2

公开(公告)日：2008-10-28

申请号：US10406592

申请日：2003-04-04

申请人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US07191373B2

公开(公告)日：2007-03-13

申请号：US10086214

申请日：2002-02-27

申请人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

IPC分类号： G01R31/28

CPC分类号： G01R31/3185 ,  G01R31/31704 ,  G01R31/31705

摘要： A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

摘要翻译： 一种用于在集成电路中插入设计调试（DFD）电路以调试或诊断DFT模块（包括扫描核心），存储器BIST（内置自检）内核，逻辑BIST核心和功能核心的方法和装置。 本发明还包括使用DFD控制器来执行多个DFD命令来调试或诊断嵌入在DFD电路中的DFT模块。 当单独使用或组合在一起时，这些DFD命令将使用低成本DFT调试器在评估板或系统上的集成电路中的DFT模块中检测或定位物理故障。 根据IEEE 1149.1边界扫描标准，进一步开发了一种计算机辅助设计（CAD）方法来合成DFD控制器和DFD电路。 DFD控制器支持但不限于以下DFD命令：RUN_SCAN，RUN_MBIST，RUN_LBIST，DBG_SCAN，DBG_MBIST，DBG_LBIST，DBG_FUNCTION，SELECT，SHIFT，SHIFT_CHAIN，CAPTURE，RESET，BREAK，RUN，STEP和STOP。

公开(公告)号：US06954887B2

公开(公告)日：2005-10-11

申请号：US10101517

申请日：2002-03-20

申请人： Laung-Terng (L.-T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

公开(公告)号：US07007213B2

公开(公告)日：2006-02-28

申请号：US10067372

申请日：2002-02-07

申请人： Laung-Terng (L.-T.) Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

发明人： Laung-Terng (L.-T.) Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

IPC分类号： G01R31/28

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

公开(公告)号：US07228479B2

公开(公告)日：2007-06-05

申请号：US11211092

申请日：2005-08-25

申请人： Chauchin Su ,  Shyh-Horng Lin ,  Laung-Terng (L.-T.) Wang

发明人： Chauchin Su ,  Shyh-Horng Lin ,  Laung-Terng (L.-T.) Wang

IPC分类号： G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/3167

摘要： An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.

摘要翻译： 基于IEEE 1149.4混合信号测试总线标准的模拟内置自检（BIST）方法。 片上产生的三角刺激通过模拟测试总线传输到被测模拟电路（CUT），它们的测试响应由双比较器进行量化。 然后将量化的结果馈送到一对计数器中以记录在判定电路中进行比较的采样计数。 然后在判定电路中产生通过/失败指示，以指示BIST操作完成后CUT的成功或失败。

公开(公告)号：US07735049B2

公开(公告)日：2010-06-08

申请号：US11350949

申请日：2006-02-10

申请人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

发明人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

IPC分类号： G06F17/50 ,  G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318547 ,  G01R31/318536

摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

公开(公告)号：US07779322B1

公开(公告)日：2010-08-17

申请号：US11898070

申请日：2007-09-07

申请人： Zhigang Wang ,  Laung-Terng (L.-T.) Wang ,  Shianling Wu ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Zhigang Jiang

发明人： Zhigang Wang ,  Laung-Terng (L.-T.) Wang ,  Shianling Wu ,  Xiaoqing Wen ,  Boryau (Jack) Sheu ,  Zhigang Jiang

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.

摘要翻译： 一种在基于扫描的集成电路中压缩包含未知值的测试响应的方法和装置。 所提出的X驱动压实机包括链切换矩阵块和空间压缩逻辑块。 链路切换矩阵块在将它们馈送到空间压缩逻辑块以进行压缩之前切换内部扫描链输出，以最小化X诱导的掩蔽和错误掩蔽。 X驱动压实机还选择性地包括有限存储器压缩逻辑块，以进一步压缩空间压缩逻辑块的输出。

公开(公告)号：US07945830B2

公开(公告)日：2011-05-17

申请号：US12776075

申请日：2010-05-07

申请人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen

发明人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US07032148B2

公开(公告)日：2006-04-18

申请号：US10876784

申请日：2004-06-28

申请人： Laung-Terng (L.-T.) Wang ,  Shun-Miin (Sam) Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

发明人： Laung-Terng (L.-T.) Wang ,  Shun-Miin (Sam) Wang ,  Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Boryau (Jack) Sheu

IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318547 ,  G01R31/318536

摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。