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    System and method for speeding up EJTAG block data transfers
    11.
    发明授权
    System and method for speeding up EJTAG block data transfers 有权
    用于加速EJTAG块数据传输的系统和方法

    公开(公告)号：US07065675B1

    公开(公告)日：2006-06-20

    申请号：US09850195

    申请日：2001-05-08

    申请人： Radhika Thekkath ,  Scott Michael McCoy ,  Franz Treue ,  Morten Zilmer ,  G. Michael Uhler

    发明人： Radhika Thekkath ,  Scott Michael McCoy ,  Franz Treue ,  Morten Zilmer ,  G. Michael Uhler

    IPC分类号： G06F11/00

    CPC分类号： G01R31/318544 ,  G01R31/31705

    摘要： A system and method for providing efficient block transfer operations through a test access port uses a Fastdata register. The Fastdata register, in part, emulates a pending process access bit (“PrAcc”) typically found in a Control register associated with the test access port. When a Fastdata access (either a Fastdata upload or a Fastdata download) is requested by a probe coupled to the test access port, the Fastdata register is serially coupled to a data register also associated with the test access port. With these registers so coupled and through the operation of the Fastdata register, downloading and uploading data can be accomplished using a single register operation.

    摘要翻译： 通过测试访问端口提供有效的块传输操作的系统和方法使用Fastdata寄存器。 Fastdata寄存器部分地模拟通常在与测试访问端口相关联的控制寄存器中找到的待处理进程访问位（“PrAcc”）。 当FastData访问（Fastdata上传或Fastdata下载）被耦合到测试访问端口的探测器请求时，Fastdata寄存器串行耦合到也与测试访问端口相关联的数据寄存器。 通过这些寄存器如此耦合，并通过Fastdata寄存器的操作，可以使用单个寄存器操作来完成下载和上传数据。

    Configurable co-processor interface
    12.
    发明授权
    Configurable co-processor interface 有权
    可配置的协处理器接口

    公开(公告)号：US07886129B2

    公开(公告)日：2011-02-08

    申请号：US10923584

    申请日：2004-08-20

    申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    IPC分类号： G06F9/312

    CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

    摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

    摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。

    Configurable co-processor interface
    13.
    发明授权
    Configurable co-processor interface 有权

    公开(公告)号：US07194599B2

    公开(公告)日：2007-03-20

    申请号：US11380925

    申请日：2006-04-29

    申请人： Lawrence H Hudepohl ,  Darren M Jones ,  Radhika Thekkath ,  Franz Treue

    发明人： Lawrence H Hudepohl ,  Darren M Jones ,  Radhika Thekkath ,  Franz Treue

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

    摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

    Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions
    16.
    发明授权
    Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions 有权
    协处理器接口同时传送多个指令以及指令的发布路径指定和/或发出命令指定

    公开(公告)号：US06754804B1

    公开(公告)日：2004-06-22

    申请号：US09753239

    申请日：2000-12-29

    申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    IPC分类号： G06F1516

    CPC分类号： G06F9/3853 ,  G06F9/3879 ,  G06F9/3885

    摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The interface groups signals that together comprises all the necessary information for a coprocessor to issue and execute instructions. Multiple issue groups are formed where each group supports different types of instructions, such as arithmetic instructions, or data transfer instructions. The coprocessor interface has an instruction transfer signal group for transferring different instructions from the CPU to the multi-issue coprocessor, sequentially or in parallel, an issue group designator for specifying an issue path within the multi-issue coprocessor for execution of the instructions, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instructions, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel.

    摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 接口组信号一起包括协处理器发出和执行指令的所有必要信息。 形成多个问题组，其中每个组支持不同类型的指令，例如算术指令或数据传输指令。 协处理器接口具有指令传送信号组，用于将不同的指令从CPU传送到多问题协处理器，顺序或并行，用于指定用于执行指令的多问题协处理器内的发布路径的问题组指示符， 忙信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个不同指令的传输，以及用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组 。

    Configurable co-processor interface
    17.
    发明授权
    Configurable co-processor interface 有权
    可配置的协处理器接口

    公开(公告)号：US07287147B1

    公开(公告)日：2007-10-23

    申请号：US09751748

    申请日：2000-12-29

    申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

    IPC分类号： G06F9/455

    CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

    摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

    摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。

    Hearing instrument using receivers with different performance characteristics
    20.
    发明授权
    Hearing instrument using receivers with different performance characteristics 有权
    听力仪器使用具有不同性能特点的接收器

    公开(公告)号：US08433072B2

    公开(公告)日：2013-04-30

    申请号：US12743211

    申请日：2008-11-07

    申请人： Christian Müller ,  Ivan Jørgensen ,  Franz Treue ,  Christian C. Bürger

    发明人： Christian Müller ,  Ivan Jørgensen ,  Franz Treue ,  Christian C. Bürger

    IPC分类号： H04R29/00 ,  H04R25/00

    CPC分类号： H04R25/658 ,  H04R25/305 ,  H04R25/604 ,  H04R25/70 ,  H04R2420/05

    摘要： The invention regards a hearing aid comprising a receiver and a signal processing device, wherein the signal processing device is electrically coupled to a connection socket operable to detachably connect the receiver to the socket and whereby the signal processing device further comprise a detector operable to detect a characteristics of the receiver which is connected to the signal processing device through the connection socket. The present invention addresses the problem of identification of individual receiver properties as well as of identifying different types of receivers.

    摘要翻译： 本发明涉及一种包括接收器和信号处理装置的助听器，其中信号处理装置电耦合到可操作以将接收器可拆卸地连接到插座的连接插座，由此信号处理装置还包括可操作以检测 通过连接插座连接到信号处理装置的接收器的特性。 本发明解决了识别各个接收机属性以及识别不同类型的接收机的问题。