公开(公告)号：US20060179237A1

公开(公告)日：2006-08-10

申请号：US11054173

申请日：2005-02-09

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  Jeffrey Stuecheli

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0851

摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.

摘要翻译： 公开了一种用于在多处理器系统中执行数据预取的方法和装置。 多处理器系统包括多个处理器，每个具有高速缓冲存储器。 缓存存储器被细分成多个片段。 一组预取请求最初由多处理器系统中的请求处理器发出。 每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。 响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。 然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。 响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。

公开(公告)号：US20080028155A1

公开(公告)日：2008-01-31

申请号：US11835259

申请日：2007-08-07

申请人： JAMES FIELDS ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： JAMES FIELDS ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0826

摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.

摘要翻译： 在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内 域。 第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播 系统按照确定。

公开(公告)号：US20070073919A1

公开(公告)日：2007-03-29

申请号：US11226967

申请日：2005-09-15

申请人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.

摘要翻译： 数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控​​制器的第二处理。 存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。 响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。 响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点 与第二个地址关联的域指示符。

公开(公告)号：US20070168618A1

公开(公告)日：2007-07-19

申请号：US11333615

申请日：2006-01-17

申请人： Leo Clark ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

发明人： Leo Clark ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。 如果分配了与存储器块相关联的地址的归属系统存储器在第一相干域内，则确定。 如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成 一致性状态下，内存块被缓存在第一个相干域之外。

公开(公告)号：US20080052471A1

公开(公告)日：2008-02-28

申请号：US11836965

申请日：2007-08-10

申请人： JAMES FIELDS, JR. ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： JAMES FIELDS, JR. ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。 高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

公开(公告)号：US20060179247A1

公开(公告)日：2006-08-10

申请号：US11055524

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.

公开(公告)号：US20060176906A1

公开(公告)日：2006-08-10

申请号：US11055366

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： H04J3/22 ,  H04J3/16 ,  H04L12/26 ,  H04J3/14

CPC分类号： G06F15/177 ,  G06F12/0831 ,  G06F12/0897

摘要： A data processing system includes a plurality of processing units coupled for communication by a communication link and a configuration register. The configuration register has a plurality of different settings each corresponding to a respective one of a plurality of different link information allocations. Information is communicated over the communication link in accordance with a particular link information allocation among the plurality of link information allocations determined by a respective setting of the configuration register.

公开(公告)号：US20060179246A1

公开(公告)日：2006-08-10

申请号：US11055483

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0826

摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.

摘要翻译： 在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内 域。 第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播 系统按照确定。

公开(公告)号：US20060179243A1

公开(公告)日：2006-08-10

申请号：US11055402

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0811 ,  G06F12/0817 ,  G06F12/0831

摘要： In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the first coherency domain to the first broadcast of the operation. If the response indicates the operation cannot be serviced in the first coherency domain alone, the master increases the scope of transmission by performing a second broadcast of the operation in both the first and second coherency domains. If the response indicates the operation can be serviced in the first coherency domain, the master refrains from performing the second broadcast, so that communication bandwidth utilized to service the operation is reduced.

摘要翻译： 在包括至少第一和第二相干域的高速缓存相干数据处理系统中，主器件在高速缓存相干数据处理系统内进行第一广播，其被限制在传输范围到第一相干域。 主机接收第一个一致性域的响应到该操作的第一次广播。 如果响应指示仅在第一个相干域中不能进行操作，则主设备通过在第一和第二相干域中执行操作的第二次广播来增加传输的范围。 如果响应指示可以在第一相干域中服务操作，则主机不执行第二广播，从而减少用于维护操作的通信带宽。

公开(公告)号：US20070239939A1

公开(公告)日：2007-10-11

申请号：US11278825

申请日：2006-04-06

申请人： Benjiman Goodman ,  Jeffrey Stuecheli

发明人： Benjiman Goodman ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6024

摘要： An apparatus for performing stream prefetch within a multiprocessor system is disclosed. The multiprocessor system includes a first and second processors, and each of the processors includes a primary cache and a secondary cache. A stream register having multiple entries is initially provided within the first processor, and at least one of the entries in the stream register includes a prefetch history field. The bit in the prefetch history field associated with a sequential address stream is set in response to the sequential address stream being found in the secondary cache of the second processor after a system memory operation has been performed by the first processor. The bit in the prefetch history field associated with the same sequential address stream is reset in response to the sequential address stream not being found in the secondary cache of the second processor after a cache memory operation has been performed by the first processor. The bit in the prefetch history field serves as a basis for a subsequent prefetch on the same sequential address stream to decide whether the data should come from a cache memory operation or a system memory operation.

摘要翻译： 公开了一种用于在多处理器系统内执行流预取的装置。 多处理器系统包括第一和第二处理器，并且每个处理器包括主缓存和次级高速缓存。 最初在第一处理器内提供具有多个条目的流寄存器，并且流寄存器中的条目中的至少一个包括预取历史字段。 响应于在由第一处理器执行系统存储器操作之后在第二处理器的辅助高速缓存中找到顺序地址流，设置与顺序地址流相关联的预取历史字段中的位。 响应于在由第一处理器执行高速缓存存储器操作之后在第二处理器的二次高速缓存中未找到顺序地址流，复位与相同顺序地址流相关联的预取历史字段中的位。 预取历史字段中的位用作相同序列地址流上的后续预取的基础，以决定数据是来自高速缓冲存储器操作还是系统存储器操作。