Apparatus and method for mapping architectural registers to physical registers
    11.
    发明授权
    Apparatus and method for mapping architectural registers to physical registers 有权
    将架构寄存器映射到物理寄存器的装置和方法

    公开(公告)号:US08578136B2

    公开(公告)日:2013-11-05

    申请号:US12801576

    申请日:2010-06-15

    IPC分类号: G06F9/30

    摘要: An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The available register identifying circuitry is arranged to reference the configuration storage, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers. This enables the performance benefits from performing register renaming to be improved, without the need to increase the number of physical registers within the physical register set.

    摘要翻译: 提供了一种用于执行寄存器重命名的装置和方法,其中来自一组架构寄存器的架构寄存器从一组物理寄存器映射到物理寄存器。 提供了可用的寄存器识别电路,其响应于设备的当前状态,以识别哪些物理寄存器形成可被寄存器重命名电路映射到可由要执行的指令指定的架构寄存器的物理寄存器池。 配置存储器存储其值在处理电路的操作期间被修改的配置数据,使得当配置数据具有第一值时,配置数据标识架构寄存器集的至少一个体系结构寄存器,其不需要映射到物理寄存器 通过寄存器重命名电路。 可用的寄存器识别电路被布置为引用配置存储器,使得当配置数据具有第一值时,由于需要映射到物理寄存器的架构寄存器的数量的减少,池中的物理寄存器的数量增加 。 这使得能够改进执行寄存器重命名的性能优势,而不需要增加物理寄存器集中的物理寄存器的数量。

    Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus
    12.
    发明申请
    Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus 有权
    用于处理发送到数据处理装置内的本地高速缓存结构的访问操作的装置和方法

    公开(公告)号:US20110314224A1

    公开(公告)日:2011-12-22

    申请号:US13067491

    申请日:2011-06-03

    IPC分类号: G06F12/08

    摘要: An apparatus and method are provided for handling access operations issued to local cache structures within a data processing apparatus. The data processing apparatus comprises a plurality of processing units each having a local cache structure associated therewith. Shared access coordination circuitry is also provided for coordinating the handling of shared access operations issued to any of the local cache structures. For a shared access operation, the access control circuitry associated with the local cache structure to which that shared access operation is issued will perform a local access operation to that local cache structure, and in addition will issue a shared access signal to the shared access coordination circuitry. For a local access operation, the access control circuitry would normally perform a local access operation on the associated local cache structure, and not notify the shared access coordination circuitry. However, if an access operation extension value is set, then the access control circuitry treats such a local access operation as a shared access operation. Such an approach ensures correction operation even after an operating system and/or an application program are migrated from one processing unit to another.

    摘要翻译: 提供了一种用于处理发送到数据处理设备内的本地高速缓存结构的接入操作的装置和方法。 数据处理装置包括多个处理单元,每个处理单元具有与其相关联的本地缓存结构。 还提供了共享访问协调电路,用于协调对任何本地高速缓存结构发布的共享访问操作的处理。 对于共享访问操作,与发布该共享访问操作的本地高速缓存结构相关联的访问控制电路将执行对该本地高速缓存结构的本地访问操作,并且另外将向共享访问协调发出共享访问信号 电路。 对于本地访问操作,访问控制电路通常将在相关联的本地高速缓存结构上执行本地访问操作,并且不通知共享访问协调电路。 然而,如果设置了访问操作扩展值,则访问控制电路将这样的本地访问操作视为共享访问操作。 即使在操作系统和/或应用程序从一个处理单元迁移到另一个处理单元之后,这种方法也确保校正操作。

    Apparatus and method for mapping architectural registers to physical registers
    13.
    发明申请
    Apparatus and method for mapping architectural registers to physical registers 有权
    将架构寄存器映射到物理寄存器的装置和方法

    公开(公告)号:US20110307681A1

    公开(公告)日:2011-12-15

    申请号:US12801576

    申请日:2010-06-15

    IPC分类号: G06F12/10

    摘要: An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical registers. Available register identifying circuitry is provided which is responsive to a current state of the apparatus to identify which physical registers form a pool of physical registers available to be mapped by register renaming circuitry to an architectural register specified by an instruction to be executed. Configuration storage stores configuration data whose value is modified during operation of the processing circuitry, such that when the configuration data has a first value, the configuration data identifies at least one architectural register of the architectural register set which does not require mapping to a physical register by the register renaming circuitry. The available register identifying circuitry is arranged to reference the configuration storage, such that when the configuration data has the first value, the number of physical registers in the pool is increased due to the reduction in the number of architectural registers which require mapping to physical registers. This enables the performance benefits from performing register renaming to be improved, without the need to increase the number of physical registers within the physical register set.

    摘要翻译: 提供了一种用于执行寄存器重命名的装置和方法,其中来自一组架构寄存器的架构寄存器从一组物理寄存器映射到物理寄存器。 提供了可用的寄存器识别电路,其响应于设备的当前状态,以识别哪些物理寄存器形成可被寄存器重命名电路映射到可由要执行的指令指定的架构寄存器的物理寄存器池。 配置存储器存储其值在处理电路的操作期间被修改的配置数据,使得当配置数据具有第一值时,配置数据标识架构寄存器集的至少一个体系结构寄存器,其不需要映射到物理寄存器 通过寄存器重命名电路。 可用的寄存器识别电路被布置为引用配置存储器,使得当配置数据具有第一值时,由于需要映射到物理寄存器的架构寄存器的数量的减少,池中的物理寄存器的数量增加 。 这使得能够改进执行寄存器重命名的性能优势,而不需要增加物理寄存器集中的物理寄存器的数量。