公开(公告)号：US20170195693A1

公开(公告)日：2017-07-06

申请号：US15468132

申请日：2017-03-24

Applicant: MEDIATEK INC.

Inventor： Sheng-Jen Wang ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04N19/91 ,  H04N19/423

CPC classification number: H04N19/91 ,  H04N19/423

Abstract: A backward adaptation apparatus includes a first storage apparatus, a count table maintenance apparatus, and a backward probability update circuit. The first storage apparatus has a first buffer and a second buffer allocated therein. The first buffer stores a first probability table involved in processing of a first frame. The second buffer stores a second probability table selectable for processing of a second frame following the first frame. The count table maintenance apparatus maintains a count table, wherein the count table maintenance apparatus has at least one count data updating circuit shared for dynamically updating the count table during the processing of the first frame. The backward probability update circuit refers to information of the count table and information of the first probability table to calculate the second probability table in the second buffer at an end of the processing of the first frame.

公开(公告)号：US09635360B2

公开(公告)日：2017-04-25

申请号：US13922481

申请日：2013-06-20

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Huei-Min Lin ,  Yung-Chang Chang ,  Chi-Cheng Ju

IPC: H04N19/86 ,  H04N19/176 ,  H04N19/117 ,  H04N19/156 ,  H04N19/82

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/156 ,  H04N19/176 ,  H04N19/82

Abstract: A method and apparatus for applying DF processing and SAO processing to reconstructed video data are disclosed. The DF processing is applied to a current access element of reconstructed video data to generate DF output data and the deblocking status is determined while applying the DF processing. Status-dependent SAO processing is applied to one or more pixels of the DF output data according to the deblocking status. The status-dependent SAO processing comprises SAO processing, partial SAO processing, and no SAO processing. The SAO starting time for SAO processing is between the DF-output starting time and ending time for the current block. The DF starting time of a next block can be earlier than the SAO ending time of the current block by a period oft, where t is smaller than time difference between the DF-output starting time and the DF starting time of the next block.

公开(公告)号：US20170019686A1

公开(公告)日：2017-01-19

申请号：US15209765

申请日：2016-07-14

Applicant: MEDIATEK INC.

Inventor： Min-Hao Chiu ,  Yu-Chuan Wang ,  Yung-Chang Chang

IPC: H04N19/60 ,  H04N19/124 ,  H04N19/176 ,  H04N19/44

CPC classification number: H04N19/60 ,  H04N19/12 ,  H04N19/547 ,  H04N19/62 ,  H04N19/88

Abstract: A partial decoding circuit with inverse second transform has a transpose buffer, a first-direction inverse residual transform circuit, and a second-direction inverse residual transform circuit. The transpose buffer stores an intermediate inverse residual transform result. The first-direction inverse residual transform circuit processes an inverse quantization output to generate the intermediate inverse residual transform result to the transpose buffer. The second-direction inverse residual transform circuit accesses the transpose buffer to retrieve the intermediate inverse residual transform result, and processes the intermediate inverse residual transform result to generate a final inverse residual transform result, where the final inverse residual transform result of the inverse second transform is further processed by an inverse transform circuit. The first-direction inverse residual transform circuit and the second-direction inverse residual transform circuit process partial residual transform data of different process units in a parallel processing manner.

Abstract translation: 具有逆第二变换的部分解码电路具有转置缓冲器，第一方向逆残差变换电路和第二方向逆残差变换电路。 转置缓冲器存储中间逆残差变换结果。 第一方向逆残差变换电路处理逆量化输出以产生到转置缓冲器的中间逆残差变换结果。 第二方向逆残差变换电路访问转置缓冲器以检索中间逆残差变换结果，并处理中间逆残差变换结果以产生最终逆残差变换结果，其中反向第二变换的最终逆残差变换结果 被逆变换电路进一步处理。 第一方向逆残差变换电路和第二方向逆残差变换电路以并行处理方式处理不同处理单元的部分残差变换数据。

公开(公告)号：US20160323589A1

公开(公告)日：2016-11-03

申请号：US15208626

申请日：2016-07-13

Applicant: MEDIATEK INC.

Inventor： Yung-Chang Chang

IPC: H04N19/186 ,  H04N19/86 ,  H04N19/117 ,  H04N19/105 ,  H04N19/139

CPC classification number: H04N19/186 ,  H04N19/105 ,  H04N19/117 ,  H04N19/132 ,  H04N19/139 ,  H04N19/182 ,  H04N19/44 ,  H04N19/86

Abstract: A video processing apparatus includes a control unit, a storage device, a video decoder and a video processor. The control unit is arranged for generating a color depth control signal. The video decoder is coupled to the storage device and the control unit, and arranged for referring to the color depth control signal to enable a target video decoding mode selected from a plurality of supported video decoding modes respectively corresponding to different output color depths, and decoding an encoded video bitstream under the target video decoding mode to generate decoded video pictures (sequence) to the storage device. The video processor is coupled to at least the storage device, and arranged for processing picture data derived from the data buffered in the storage device to generate output video pictures (sequence) to a display apparatus.

Abstract translation: 视频处理装置包括控制单元，存储装置，视频解码器和视频处理器。 控制单元被布置用于产生颜色深度控制信号。 视频解码器耦合到存储装置和控制单元，并且被配置为参考色深控制信号，以便能够分别对应于不同输出颜色深度的多个支持的视频解码模式中选择的目标视频解码模式，以及解码 在目标视频解码模式下的编码视频比特流，以产生解码的视频图像（序列）到存储设备。 视频处理器至少耦合到存储设备，并且被布置用于处理从缓冲在存储设备中的数据导出的图像数据，以向显示设备生成输出视频图像（序列）。

公开(公告)号：US20160241854A1

公开(公告)日：2016-08-18

申请号：US15016221

申请日：2016-02-04

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/13 ,  H04N19/91 ,  H04N19/895 ,  H04N19/176 ,  H04N19/436 ,  H04N19/44 ,  H04N19/48

CPC classification number: H04N19/91

Abstract: An apparatus and method for high-throughput entropy decoding in a video decoder are disclosed. The apparatus comprises an arithmetic decoding processing circuitry and a variable-length decoder (VLD). The arithmetic decoding processing circuitry receives a video bitstream through a bitstream input, applies arithmetic decoding to at least a portion of the video bitstream to derive one or more arithmetic-decoded binary strings containing no arithmetic encoded binary string, and stores the arithmetic-decoded binary strings in the storage device. The variable-length decoder (VLD) is coupled to the arithmetic decoding processing circuitry, the storage device and a VLD output. The variable-length decoder receives at least a portion of arithmetic-decoded bitstream when arithmetic-decoded bitstreams stored in the storage device are complete for a selected image unit, decodes at least a portion of arithmetic-decoded bitstream into one or more decoded syntax elements, and provides the decoded syntax elements through the VLD output.

Abstract translation: 公开了一种用于视频解码器中高吞吐量熵解码的装置和方法。 该装置包括算术解码处理电路和可变长度解码器（VLD）。 算术解码处理电路通过比特流输入接收视频比特流，对视频比特流的至少一部分应用算术解码以导出不包含算术编码二进制串的一个或多个算术解码二进制串，并存储算术解码二进制码 存储设备中的字符串。 可变长度解码器（VLD）耦合到算术解码处理电路，存储设备和VLD输出。 可变长度解码器在对存储设备中存储的算术解码比特流对于所选择的图像单元是完整的时，接收算术解码比特流的至少一部分，将至少一部分算术解码的比特流解码为一个或多个解码的语法元素 ，并通过VLD输出提供经解码的语法元素。

公开(公告)号：US20140192899A1

公开(公告)日：2014-07-10

申请号：US14142929

申请日：2013-12-30

Applicant: MEDIATEK INC.

Inventor： Chih-Ming Wang ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/593 ,  H04N19/174

CPC classification number: H04N19/70 ,  H04N19/169 ,  H04N19/174 ,  H04N19/44

Abstract: A tile processing method includes at least the following steps: parsing a bitstream of at least a multi-tile picture for deriving bitstream address related information from a segment header of at least a specific segment of the multi-tile picture; and utilizing a tile processing circuit for receiving at least the bitstream address related information and referring to at least the received bitstream address related information to determine a bitstream start address of a specific tile of the multi-tile picture.

Abstract translation: 瓦片处理方法至少包括以下步骤：解析至少多瓦片图像的比特流，以从多瓦片图片的至少特定片段的片段标题导出比特流地址相关信息; 以及利用瓦片处理电路来至少接收所述比特流地址相关信息，并且至少参考所接收的比特流地址相关信息，以确定所述多瓦片图像的特定瓦片的位流起始地址。

公开(公告)号：US20140133580A1

公开(公告)日：2014-05-15

申请号：US14165599

申请日：2014-01-28

Applicant: MEDIATEK INC.

Inventor： Yung-Chang Chang ,  Chia-Yun Cheng ,  Chi-Cheng Ju

IPC: H04N19/44

CPC classification number: H04N19/00533 ,  H04N19/423 ,  H04N19/433 ,  H04N19/44 ,  H04N19/577 ,  H04N19/59

Abstract: A video decoding method for decoding a bit stream to a plurality of frames, applied in a video decoding system, includes: determining whether a size of a current picture is equal to that of a next picture according to the bit stream; scaling a corresponding reference frame for the next picture to generate a scaled frame when the size of the current picture is not equal to that of the next picture; and storing the scaled frame in a first buffer of a storage unit, wherein at least a portion of a first frame originally stored in the first buffer is used; wherein when it is determined that the size of the current picture is not equal to that of the next picture, the next picture is encoded in the bit stream in a mode that the scaled corresponding reference frame is required for decoding the next picture.

Abstract translation: 一种视频解码方法，用于将应用于视频解码系统的比特流解码为多个帧，包括：根据比特流确定当前图像的大小是否等于下一图像的大小; 当当前图像的大小不等于下一图像的大小时，缩放下一图像的对应参考帧以产生缩放帧; 并且将缩放的帧存储在存储单元的第一缓冲器中，其中使用原始存储在第一缓冲器中的第一帧的至少一部分; 其中当确定当前画面的尺寸不等于下一画面的尺寸时，下一画面以对于下一画面进行解码所需的缩放对应的参考帧的模式被编码在比特流中。

公开(公告)号：US20140036992A1

公开(公告)日：2014-02-06

申请号：US13922481

申请日：2013-06-20

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Huei-Min Lin ,  Yung-Chang Chang ,  Chi-Cheng Ju

IPC: H04N7/26

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/156 ,  H04N19/176 ,  H04N19/82

Abstract: A method and apparatus for applying DF processing and SAO processing to reconstructed video data are disclosed. The DF processing is applied to a current access element of reconstructed video data to generate DF output data and the deblocking status is determined while applying the DF processing. Status-dependent SAO processing is applied to one or more pixels of the DF output data according to the deblocking status. The status-dependent SAO processing comprises SAO processing, partial SAO processing, and no SAO processing. The SAO starting time for SAO processing is between the DF-output starting time and ending time for the current block. The DF starting time of a next block can be earlier than the SAO ending time of the current block by a period oft, where t is smaller than time difference between the DF-output starting time and the DF starting time of the next block.

Abstract translation: 公开了一种用于对重构的视频数据应用DF处理和SAO处理的方法和装置。 DF处理被应用于重构的视频数据的当前访问元件以产生DF输出数据，并且在应用DF处理的同时确定去块状态。 根据去块状态，将状态依赖的SAO处理应用于DF输出数据的一个或多个像素。 状态依赖性SAO处理包括SAO处理，部分SAO处理，无SAO处理。 SAO处理的SAO启动时间在当前块的DF输出开始时间和结束时间之间。 下一个块的DF开始时间可以比当前块的SAO结束时间早一个时间t，其中t小于DF输出开始时间和下一个块的DF开始时间之间的时间差。

公开(公告)号：US20140022344A1

公开(公告)日：2014-01-23

申请号：US14035962

申请日：2013-09-25

Applicant: MEDIATEK INC.

Inventor： Te-Chi Hsiao ,  Yung-Chang Chang ,  Ching-Chieh Wang ,  Shih-Hung Lin ,  Chi-Cheng Ju

IPC: H04N13/00

CPC classification number: H04N13/161 ,  H04N19/30 ,  H04N19/44 ,  H04N19/597 ,  H04N21/234327

Abstract: An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.

Abstract translation: 包括第一比特流和第二比特流的输入视频比特流的示例性解码方法包括：对第一比特流中的第一图像进行解码; 在从第一图像解码得到的所需解码数据准备好进行第一比特流中的第二图像的第一解码操作之后，执行第一解码操作; 并且在从第一图像的解码得到的所需解码数据准备好进行第二比特流中的图像的第二解码操作之后，执行第二解码操作，其中对第一比特流中的第二图像进行解码的时间段和时间段 对第二位流中的图像进行解码的时间重叠。

公开(公告)号：US20200213624A1

公开(公告)日：2020-07-02

申请号：US16815957

申请日：2020-03-11

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/82 ,  H04N19/42 ,  H04N19/423

Abstract: Aspects of the disclosure provide a method and a circuit for adaptive loop filtering in a video coding system. The method can include receiving a block of samples generated from a previous-stage filter circuit in a filter pipeline, the block of samples being one of multiple blocks included in a current picture, performing, in parallel, adaptive loop filter (ALF) processing for multiple target samples in the block of samples, while the previous-stage filter circuit is simultaneously processing another block in the current picture, storing, in a buffer, first samples each having a filter input area defined by a filter shape that includes at least one sample which has not been received, and storing, in the buffer, second samples included in the filter input areas of the first samples.