公开(公告)号：US20190073217A1

公开(公告)日：2019-03-07

申请号：US15694893

申请日：2017-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Uria Basher

IPC: G06F9/30 ,  H04L9/06

Abstract: Instruction code is executed in a central processing unit of a network computing device. Besides the central processing unit the device is provided with a code sequencer operative to execute predefined instruction sequences. The code sequencer is invoked by a trigger instruction in the instruction code, which is encountered by the central processing unit. Responsively to its invocations the code sequencer executes the predefined instruction sequences.

公开(公告)号：US20240406148A1

公开(公告)日：2024-12-05

申请号：US18626354

申请日：2024-04-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Uria Basher ,  Michael Tahar ,  Amir Modan ,  Ben Witulski ,  Miriam Menes ,  Miri Shtaif

IPC: H04L9/40

Abstract: In one embodiment, a system includes a networking device including a network interface to receive network packets having headers including datagram transport layer security (DTLS) headers from a remote device over a packet data network, packet processing circuitry to identify first packets of the received packets for DTLS processing in the packet processing circuitry, identify second packets of the received packets to bypass DTLS processing in the packet processing circuitry and to be provided to software to perform DTLS processing on the second packets, and perform DTLS processing on the first packets, and a host interface to provide the DTLS processed first packets to the software, and provide the second packets to the software to perform DTLS processing on the second packets.

公开(公告)号：US20240394060A1

公开(公告)日：2024-11-28

申请号：US18321013

申请日：2023-05-22

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Shahar ,  Avi Urman ,  Omri Kahalon ,  Uria Basher ,  Doron Haim ,  Sagi Farjun

IPC: G06F9/30 ,  G06F9/38

Abstract: A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.

公开(公告)号：US12131132B2

公开(公告)日：2024-10-29

申请号：US17180993

申请日：2021-02-22

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72

CPC classification number: G06F7/728

Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.

公开(公告)号：US10599441B2

公开(公告)日：2020-03-24

申请号：US15694893

申请日：2017-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Uria Basher

IPC: G06F9/30 ,  H04L9/06 ,  G06F9/38 ,  G06F12/0875

Abstract: Instruction code is executed in a central processing unit of a network computing device. Besides the central processing unit the device is provided with a code sequencer operative to execute predefined instruction sequences. The code sequencer is invoked by a trigger instruction in the instruction code, which is encountered by the central processing unit. Responsively to its invocations the code sequencer executes the predefined instruction sequences.

公开(公告)号：US20200026814A1

公开(公告)日：2020-01-23

申请号：US16038207

申请日：2018-07-18

Applicant: Mellanox Technologies, Ltd.

Inventor： Uria Basher ,  Anton Rozen

IPC: G06F17/50

Abstract: A method for designing a logic circuit includes providing an initial design of the logic circuit, including at least first and second logic stages, and a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch. Timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed, are estimated. Based on the timing delays, a decision is made whether the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit. A final design of the logic circuit is then generated, in which the sequential component is either bypassed or not bypassed, depending on the decision.